Kuojun Yang

A seamless acquisition digital storage oscilloscope with three-dimensional waveform display

In traditional digital storage oscilloscope (DSO), sampled data need to be processed after each acquisition. During data processing, the acquisition is stopped and oscilloscope is blind to the input signal. Thus, this duration is called dead time. With the rapid development of modern electronic systems, the effect of infrequent events becomes significant. To capture these occasional events in shorter time, dead time in traditional DSO that causes the loss of measured signal needs to be reduced or even eliminated. In this paper, a seamless acquisition oscilloscope without dead time is proposed. In this oscilloscope, three-dimensional waveform mapping (TWM) technique, which converts sampled data to displayed waveform, is proposed. With this technique, not only the process speed is improved, but also the probability information of waveform is displayed with different brightness. Thus, a three-dimensional waveform is shown to the user. To reduce processing time further, parallel TWM which processes several sampled points simultaneously, and dual-port random access memory based pipelining technique which can process one sampling point in one clock period are proposed. Furthermore, two DDR3 (Double-Data-Rate Three Synchronous Dynamic Random Access Memory) are used for storing sampled data alternately, thus the acquisition can continue during data processing. Therefore, the dead time of DSO is eliminated. In addition, a double-pulse test method is adopted to test the waveform capturing rate (WCR) of the oscilloscope and a combined pulse test method is employed to evaluate the oscilloscopes capture ability comprehensively. The experiment results show that the WCR of the designed oscilloscope is 6,250,000 wfms/s (waveforms per second), the highest value in all existing oscilloscopes. The testing results also prove that there is no dead time in our oscilloscope, thus realizing the seamless acquisition.

Timing Skew Calibration Method for TIADC-Based 20 GSPS Digital Storage Oscilloscope

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). When input signal frequency is very high, timing skews have significant effect on distortion. Therefore, a new timing skew calibration method is proposed in this paper. This method is based on the truth that timing skews are related to the product of the outputs of sub-ADCs. After timing skews are estimated, the digital controlled delay elements (DCDE) in ADC and phase locked loop (PLL) are utilized to calibrate timing skews. No auxiliary circuit and digital filter are needed for this calibration method. Simulation results show that the proposed method can estimate timing skew accurately. It is also proved that an accurate estimation can be obtained even the signal to noise ratio (SNR) of input signal is 20dB. The proposed method is employed to calibrate timing skews in a 16-channel TIADC-based 20GSPS digital storage oscilloscope (DSO). The experiment results demonstrate the usefulness of the proposed method. We can see that after timing skews are calibrated, the spectrum spurs have been effectively eliminated.

A Statistic-Based Calibration Method for TIADC System

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5u2009GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20u2009dB. Furthermore, the results obtained from a real four-channel 5u2009GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.

Information Entropy- and Average-Based High-Resolution Digital Storage Oscilloscope

Vertical resolution is an essential indicator of digital storage oscilloscope (DSO) and the key to improving resolution is to increase digitalizing bits and lower noise. Averaging is a typical method to improve signal to noise ratio (SNR) and the effective number of bits (ENOB). The existing averaging algorithm is apt to be restricted by the repetitiveness of signal and be influenced by gross error in quantization, and therefore its effect on restricting noise and improving resolution is limited. An information entropy-based data fusion and average-based decimation filtering algorithm, proceeding from improving average algorithm and in combination with relevant theories of information entropy, are proposed in this paper to improve the resolution of oscilloscope. For single acquiring signal, resolution is improved through eliminating gross error in quantization by utilizing the maximum entropy of sample data with further noise filtering via average-based decimation after data fusion of efficient sample data under the premise of oversampling. No subjective assumptions and constraints are added to the signal under test in the whole process without any impact on the analog bandwidth of oscilloscope under actual sampling rate.

Analysis of Channel Mismatch Errors in Frequency-Interleaved ADC System

Frequency-interleaved ADC (FIADC) is less sensitive to the mismatches between channels than the time-interleaved ADC (ADC). However, channel mismatches in FIADC such as offset, gain, and timing mismatches among channel ADCs still degrade the performance of the FIADC system. This paper analyzes the channel mismatch effects in the FIADC system. Based on the analysis, we have clarified that the gain mismatch errors and timing mismatch errors result in noises with the same frequency but different phases, and only the magnitudes of noises due to the offset mismatch errors do not depend on the input frequency. The analyzed results can be used for calibration algorithms to compensate for the channel mismatch errors among the FIADC channels.

A high speed random equivalent sampling method based on time-stretch

Random equivalent sampling is realized based on time stretch in this paper. Firstly, the measuring error of time stretch factor K is analyzed. Formulas are derived to describe the effect of measuring error of K and jitter on the waveform reconstruction. According to the formulas, multiple measurements are used to reduce the measuring error of K, and average filter is utilized to reduce the distortion introduced by jitter. The effectiveness of average filter is verified through simulation. And the proposed methods are implemented in digital oscilloscope, the experiment results prove that our method is useful and the equivalent sampling rate reaches 100GSPS.

Digital Estimation and Compensation of Analog Errors in Frequency-Interleaved ADCs

A novel digital compensation scheme for measuring, estimating and correcting linear weakly time-varying analog errors in frequency-interleaved analog-to-digital converters (FI-ADCs) is presented. T...