Shulin Tian

Timing Skew Calibration Method for TIADC-Based 20 GSPS Digital Storage Oscilloscope

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). When input signal frequency is very high, timing skews have significant effect on distortion. Therefore, a new timing skew calibration method is proposed in this paper. This method is based on the truth that timing skews are related to the product of the outputs of sub-ADCs. After timing skews are estimated, the digital controlled delay elements (DCDE) in ADC and phase locked loop (PLL) are utilized to calibrate timing skews. No auxiliary circuit and digital filter are needed for this calibration method. Simulation results show that the proposed method can estimate timing skew accurately. It is also proved that an accurate estimation can be obtained even the signal to noise ratio (SNR) of input signal is 20dB. The proposed method is employed to calibrate timing skews in a 16-channel TIADC-based 20GSPS digital storage oscilloscope (DSO). The experiment results demonstrate the usefulness of the proposed method. We can see that after timing skews are calibrated, the spectrum spurs have been effectively eliminated.

Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs

In data acquisition systems, with help of time-interleaved analog-to-digital converter (TIADC) architecture, the maximum sample rate of the whole system can be increased efficiently. However, inevitable offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the sampling performance. In order to develop the mismatched TIADC structure, this paper first proposes a new time-domain algorithm to estimate the three aforementioned mismatch errors, and then puts forward a calibration method to calibrate the mismatch errors. Finally, numerical simulations are presented to verify the proposed estimation and calibration algorithm.

Analysis of Channel Mismatch Errors in Frequency-Interleaved ADC System

Frequency-interleaved ADC (FIADC) is less sensitive to the mismatches between channels than the time-interleaved ADC (ADC). However, channel mismatches in FIADC such as offset, gain, and timing mismatches among channel ADCs still degrade the performance of the FIADC system. This paper analyzes the channel mismatch effects in the FIADC system. Based on the analysis, we have clarified that the gain mismatch errors and timing mismatch errors result in noises with the same frequency but different phases, and only the magnitudes of noises due to the offset mismatch errors do not depend on the input frequency. The analyzed results can be used for calibration algorithms to compensate for the channel mismatch errors among the FIADC channels.

A high speed random equivalent sampling method based on time-stretch

Random equivalent sampling is realized based on time stretch in this paper. Firstly, the measuring error of time stretch factor K is analyzed. Formulas are derived to describe the effect of measuring error of K and jitter on the waveform reconstruction. According to the formulas, multiple measurements are used to reduce the measuring error of K, and average filter is utilized to reduce the distortion introduced by jitter. The effectiveness of average filter is verified through simulation. And the proposed methods are implemented in digital oscilloscope, the experiment results prove that our method is useful and the equivalent sampling rate reaches 100GSPS.

Digital Estimation and Compensation of Analog Errors in Frequency-Interleaved ADCs

A novel digital compensation scheme for measuring, estimating and correcting linear weakly time-varying analog errors in frequency-interleaved analog-to-digital converters (FI-ADCs) is presented. T...