Kwang-du Lee

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.

High efficiency 5GHz CMOS power amplifier with adaptive bias control circuit

A 5 GHz automatically bias controlled power amplifier is manufactured in a 0.18 /spl mu/m CMOS process and occupies 0.54 mm/sup 2/. The measured power gain, P/sub 1dB/, and PAE are 7.1 dB, 19.2 dBm, and 17.5%, respectively. For fair comparison, the same PA without the bias circuit is also implemented. The fully integrated bias control circuit improves the power efficiency by 21% at 13 dBm output power. Moreover, the P1dB is also improved from 18.3 dBm to 19.2 dBm.

A 2.4GHz/5.2GHz CMOS power amplifier for dual-band applications

A 2.4GHz/5.2GHz CMOS dual band power amplifier is presented in this work. In order to design high power CMOS amplifier, various power NMOS transistor cells are scrutinized. Considering small signal and large signal characteristics of power NMOS cell, 2/spl times/128/spl times/5/spl mu/m cell is chosen for our dual band PA. A modified macro model is used for the simulation accuracy. As for selecting desired band, there are band-switched matching networks on both input and load of the first stage amplifier, which is followed by NMOS SPDT switch. At 2.4Ghz and 5.2GHz bands, the achieved values of Psat are 9.7dBm and 19.5dBm, respectively. In case of PAE, we obtain 15.3% at 5.2GHz.