KwangSeok Kim

A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier

This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.

A Time-Domain High-Order MASH

In this paper, a time-domain high-order ΔΣ analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order ΔΣ ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.

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In this paper, we fabricated high-Q inductors on anodized aluminum substrate using low-k benzocyclobutene (BCB) as an interlayer and thick Cu plating process. The 2 nH inductors on 80 mum anodized aluminum have Q-factor as high as 30 at 2 GHz and self-resonant frequency as high as 11 GHz. Anodized aluminum substrate is useful and cost-effective for high power packaging because of high thermal conductivity. Image current arises on anodized aluminum substrate because aluminum as a conductor is closely located below spiral inductors on anodized aluminum (Al2 O3) layer. Inductances of spiral inductors were calculated considering image current through Grovers method. Thus, the influence of image current on inductance confirmed through quantitative analysis

ADC Using Voltage-Controlled Gated-Ring Oscillator

This paper presents a second-order ΔΣ time-to-digital converter (TDC) by using a switched-ring oscillator (SRO) and a gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using SROs, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the oscillators. Furthermore, the performance of the proposed TDC is analyzed, including non-idealities such as phase noise, mismatch, and PVT variations. The prototype 1-1 MASH TDC achieves 148 f srms integrated noise in 4 MHz signal bandwidth at 400 MS/s while consuming 6.55 mW in a 65 nm CMOS process.

Fabrication and Analysis of High-Q Inductor on Anodized Aluminum for High Power Package

In this paper, a time-domain analog-to-digital converter (ADC) using time-to-digital converter (TDC) is presented. The use of TDC in ADCs is a promising technique for future scaled CMOS processes, as it relies on time-resolution rather than voltage resolution. In the proposed ADC, a single-slope capacitor-discharge method is employed to convert input voltage into time, which relaxes the time-domain linearity requirement of comparator. In addition, time-interleaving is employed to increase the time resolution. Lastly, a shared counter-based TDC is used for compact and simple time quantization. Simulation results in 0.25μm CMOS shows the feasibility of the proposed architecture.

A 148fs rms Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator.

In this paper, an analysis of the effect of time-variant reflected impedance and its detection method on wireless power transfer(WPT) systems are presented. The reflected resistance at WPT systems is very important parameter as it indicates how well matched antenna is and will exhibit high efficiency. Proposed detection method is based on transmitter current variation analysis with respect to frequency sweep. Using the proposed design method, a wireless power transfer system operating at the frequency of 125 kHz, is design and detect reflected impedance variation. The proposed design method provides good agreements between measured and simulated results. Therefore, The proposed detecting method provides a nonintrusive method to detect harmful object in WPT system.

Time-interleaved single-slope ADC using counter-based time-to-digital converter

This paper presents an all-digital second-order ΔΣ time-to-digital converter (TDC) by using switched-ring oscillator (SRO) and gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using the SRO, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the SROs. The prototype TDC achieves 148fsrms integrated noise and 80.4dB dynamic range in 4MHz signal bandwidth at 400MS/s while consuming 6.55mW in a 65nm CMOS process.