Wonsik Yu

A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-amplifier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while consuming 15.4 mW. Compared to other high-resolution state-of-the-art TDCs, the proposed pipelined TDC achieves the best figure-of-merit (FoM) without any calibration.

A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier

This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.

A Time-Domain High-Order MASH

In this paper, a time-domain high-order ΔΣ analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order ΔΣ ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.

\Delta\Sigma

In this paper, a fourth-order ΔΣ time-to-digital converter (TDC) is proposed to achieve high resolution and wide signal bandwidth. The proposed TDC is based on a 1-3 multi-stage-noise-shaping (MASH) architecture, where the first-stage is a gated-ring oscillator based TDC (GRO-TDC) and the second-stage is a single-loop third-order ΔΣ TDC based on a time-domain error-feedback filter using time registers, time adders and time amplifiers. Implemented in 65 nm CMOS process, the prototype TDC achieves 0.22 psrms of integrated noise within 15 MHz signal bandwidth at 300 MS/s while consuming lower than 6.24 mW. The proposed TDC occupies an active die area of only 0.03 mm2.

ADC Using Voltage-Controlled Gated-Ring Oscillator

This paper presents a second-order ΔΣ time-to-digital converter (TDC) by using a switched-ring oscillator (SRO) and a gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using SROs, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the oscillators. Furthermore, the performance of the proposed TDC is analyzed, including non-idealities such as phase noise, mismatch, and PVT variations. The prototype 1-1 MASH TDC achieves 148 f srms integrated noise in 4 MHz signal bandwidth at 400 MS/s while consuming 6.55 mW in a 65 nm CMOS process.

A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter

One of the recent trends in multimode multiband (MMMB) receivers is to remove the analog filter or variable-gain amplifier (VGA) in the receiver chain and employ a wide-dynamic-range ADC directly after the mixer or include the mixer in the ADC [1,2]. While such architecture provides ease of programmability once the signals are digitized, it puts a large burden on the ADC and anti-alias filter. Hence, ADCs typically use high-performance analog circuits for wide dynamic range, even though it is difficult to implement these circuits using low-voltage nanoscale CMOS processes. A promising ADC architecture for an MMMB receiver is the VCO-based ADC, since it offers 1st-order noise-shaping from its open-loop digital-intensive nature, thus allowing high sampling rate and high SNR [3]. Furthermore, the VCO-based ADC provides an inherent anti-aliasing 1st-order Sinc filter due to the innate integrating ability of the VCO [4]. Unfortunately, for multiband receivers that do not have an RF pre-filter, a Sinc filter alone does not provide enough out-of-band rejection and hence higher-order anti-aliasing filters are required. In order to solve this problem, we propose a 2nd-order anti-aliasing Sinc filter (Sinc2 filter) that provides double the rejection ratio of a Sinc filter. Furthermore, the proposed technique is highly digital and can be embedded in a VCO, resulting in little overhead.

A 148fs rms Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator.

In this brief, an energy-efficient time-to-digital converter (TDC) using a hybrid of time- and voltage-domain circuits is presented. The proposed TDC operates in two steps, i.e., first in the time domain by using a delay-line TDC and then in the voltage domain by using a successive-approximation-register analog-to-digital converter. The time residue of the first stage is converted to voltage by using a switch-based time-to-voltage converter (TVC) that eliminates the need for a current source with large output impedance. To improve the linearity of the proposed TVC, pseudodifferential time-domain signaling is presented. A prototype chip fabricated in the 65-nm CMOS achieves 630 fs of time resolution at 120 megasamples/s while consuming 3.7 mW from a 1.2-V supply. The figure of merit is 244 fJ/conversion-step, which is the best among the recently published high-speed TDCs.

A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS

In this paper, we present a 0.2-1.8-GHz digital-intensive receiver front-end using a voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) running at 1.4 Gs/s in 90-nm CMOS. To improve the out-of-band rejection, we propose a second-order anti-aliasing Sinc filter that can be embedded in the ADC, which exploits the integrating nature of a VCO. the nonideal effect of the proposed architecture is analyzed with regard to the waveform imperfection due to device mismatch. The proposed receiver achieves -94 dBm of sensitivity at 1-MHz bandwidth and - 6.8 dBm of IIP3, while providing 50-dB rejection of aliased signals.

A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC

This paper presents an all-digital second-order ΔΣ time-to-digital converter (TDC) by using switched-ring oscillator (SRO) and gated switched-ring oscillator (GSRO). Unlike conventional multi-stage noise-shaping (MASH) TDC using the SRO, the proposed TDC does not require complex calibration to compensate for the error from frequency difference between the SROs. The prototype TDC achieves 148fsrms integrated noise and 80.4dB dynamic range in 4MHz signal bandwidth at 400MS/s while consuming 6.55mW in a 65nm CMOS process.