Kwon Chul Park

QoS evaluation of KT-NGN

KT is considering the installation of a new IP router with a backbone network for implementation of NGN. QoS discussions on whether the IP router satisfies the forthcoming NGN customers who use basic and application NGN services still remain. QoS values as packet delay, packet loss and jitter are measured and analyzed at the KT-NGN test bed, and are compared with the ITU-T QoS recommendation values. Most of the measured QoS values are within ITU-T recommendations so we can assert that KT decision of IP router for NGN backbone installation is correct.

VoIP interoperation with KT-NGN

KT has started NGN implementation by replacement of old switching system that have no No.7 signaling and caller identification functions with Access gateway. While, KT-VoIP service of H323 and SIP based protocols has been developed with many attractive services, but actual interoperation between NGN and VoIP network will be started mid. of 2004 at the second stage of NGN. KT needs to have specific implementation plan for interoperation between NGN and VoIP network and should consider many issues as certification, charging, security, numbering, routing and sewer operation. Here, certification and charging issues are mentioned and overall service now of VoIP and NGN after second stage of KT-NGN is shown.

Reconfigurable shared buffer ATM switch

This paper describes the architecture of a reconfigurable shared buffer asynchronous transfer mode (ATM) switch and its VLSI implementation. The reconfigurable shared buffer ATM switch on one chip has a shared buffer of 4 ns scalable pipelined memory. It solves the restriction of memory cycle time in a shared buffer ATM switch, and supports flexible switching performance by the scalability of the embedded buffer. The proposed switch provides port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the proposed ATM switch can be reconfigured without serious circuit redesign. Prototype chip has been designed for 4/spl times/4 ATM switch that has a shared buffer of 128-cell. It is integrated in 10.6/spl times/10.6 mm/sup 2/ with 0.6 /spl mu/m twin well, double-metal, and single-poly CMOS technology. Simulated operating frequency is 80 MHz which supports 640 Mbps per port.