Kwong-Tak Chui

A low-cost 300 MHz RISC CPU with attached media processor

This custom CPU derived from the StrongARM/sup TM/ 110 is capable of more than 2 billion 16 b operations per second (2 BOPs). Starting with the original design, an attached media processor (AMP) is integrated along with a synchronous DRAM memory controller and separate I/O bus. In addition, several enhancements are made to the CPU and cache subsystem and the chip is reduced from 0.35 /spl mu/m to 0.28 /spl mu/m technology. The chip includes 3.3M transistors and measures 60 mm/sup 2/. It dissipates less than 3 W at 300 MHz at 2.0 V internal, 3.3 V I/O. The chip supports dynamic clock frequency switching for reduced operating power during low performance demands. There are 333 separately conditioned clocks on the chip. For battery powered applications, Vdd is reduced to achieve <0.5 W operation at 150 MHz. The chip is pseudo-static and supports clock stop and IDDQ testing.

Communication performance of a modular high-bandwidth multiprocessor system

This article deals with communication performance of a multiprocessor system implemented using award-wining BCM 1480 multi-core chips. Our system uses high-performance HyperTransport links to interconnect constituent chips, realizing cache-coherent non-uniform memory access. It takes advantage of hardware support from the BCM 1480 chip to attain very impressive communication performance among constituent BCM 1480 chips. This is achieved via an extension to global memory, so that small messages can be pushed quickly across chips in less than one us by the CPU cores through DMA to achieve zero-copy message buffering. It eliminates all overhead associated with the kernel and protocol processing for the utmost interconnect bandwidth in data transfers.