Kye-Shin Lee

A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications

A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel SigmaDelta modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The SigmaDelta modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal bandwidth with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18-mum CMOS technology using metal-insulator-metal capacitors. The total power consumption of the SigmaDelta modulator is 5.4mW from a 1.8-V supply and occupies an active area of 1.1 mm2

Time-interleaved sigma-delta modulator using output prediction scheme

A time-interleaved sigma-delta modulator using the output prediction scheme is proposed. This approach uses only one integrator channel along with incomplete integrator output terms to eliminate the quantizer domino which is a key limit for practical circuit implementation of conventional time-interleaved sigma-delta modulators. In addition, channel mismatch effects due to mismatch within multiple integrator feedback paths can be reduced by optimizing the feedback path. An equivalent two-channel time-interleaved version of the conventional second-order sigma-delta modulator is realized to verify the proposed method.

Fabric Nanocomposite Resistance Temperature Detector

This paper illustrates the characterization of a fabric resistance temperature (RTD) detector made from electrospun nylon-6 functionalized with multiwalled carbon nanotubes (MWCNTs) and polypyrrole (PPy) for use in supracutaneous applications like smart clothing, prosthetic sockets, and other medical devices where a temperature detecting fabric is better suited than a rigid detector. The nanocomposite material acts like a RTD, because the conductivity increases linearly with temperature. The empirically determined temperature coefficient of resistance (TCR) is reported for this material, and is -0.204 ± 0.008%/C. Development of a simple and scalable process for constructing the detector utilized electrospinning nylon-6 as a membrane style substrate, vacuum filtration of MWCNTs onto the nylon scaffold, and vapor phase polymerization of pyrrole to PPy onto the MWCNT functionalized nylon nanofibers. The optimal loading of MWCNTs is 6.6 wt%. The conductivity of the device follows a percolative behavior and TCR values indicate this is a viable option for temperature detection. Resistance decreases with increasing temperature, which indicates this is a negative TCR material.

SC amplifier and SC integrator with an accurate gain of 2

A fully differential switched-capacitor (SC) amplifier and integrator with an accurate gain of 2 are proposed. Both circuits are based on a novel capacitor mismatch compensation scheme which uses the same capacitor as the charge sampling and summing element. Therefore, the gain error which is linearly proportional to the capacitor mismatch in conventional SC circuits becomes proportional to the square of the mismatch. In addition, the proposed scheme does not require additional active blocks, and the valid output is generated within two clock cycles.

Domino free 4-path time-interleaved second order sigma-delta modulator

A domino free 4-path time-interleaved second order sigma-delta modulator is proposed. This time-interleaved scheme uses only one integrator channel along with incomplete integrator output terms to completely eliminate the quantizer domino which is a key limit for the practical circuit implementation of conventional multi-path time-interleaved sigma-delta modulators. In addition, the single integrator channel leads to considerable hardware reduction as well as path mismatch insensitivity, since only one global feedback path is required. As a result, the switched capacitor implementation of the 4-path time-interleaved second order sigma-delta modulator is enabled with the conventional 2-phase clocking scheme by using only 5 op-amps.

Mixed CT/DT Cascaded Sigma-Delta Modulator

A mixed CT/DT 2-1 cascaded ΣΔM which includes a first stage CT ΣΔM and a second stage mismatch insensitive two-channel time-interleaved DT ΣΔM is proposed. With this approach, the advantages of both CT and DT ΣΔMs including high speed operation, inherent anti-aliasing filter, and good coefficient matching can be achieved. The twochannel time-interleaved ΣΔM used in the second stage alleviates the speed constraints of the DT ΣΔM, whereas enables better matching between the analog and digital filter coefficients compared to CT ΣΔMs.

A Wide Linear Output Range Biopotential Amplifier for Physiological Measurement Frontend

This paper presents a wide linear output range biopotential amplifier for physiological measurement frontend. The proposed amplifier consists of an open-loop rail-to-rail differential pair in the first stage and a closed-loop common source amplifier in the second stage, which extends the linear output range by maintaining a constant voltage gain with amplifier output level variation. The nMOS and pMOS gain enhancement switches provide additional compensation for the voltage gain degradation as the amplifier output level moves toward the supply rails. In addition, voltage buffers are used after the first and second stages to alleviate the loading effect. This enables using small-sized feedback resistors, where the amplifier performance is relatively insensitive to resistor mismatch. Aside from the wide linear output range, this approach leads to small silicon area, low power, and relatively high common mode rejection ratio and power supply rejection ratio, which are highly demanding for portable and implantable biomedical instrumentation frontend. The proposed amplifier is implemented using CMOS 0.35μm technology (3.3 V supply) with core area of 0.063 mm2. Measurement results show a stable voltage gain of 46.3 dB for amplifier output range from 0.15 to 3.12 V, and a 0.04% total harmonic distortion with input amplitude of 15 mVpp. Furthermore, the amplifier operation is demonstrated with an actual ECG measurement setup.

SAR ADC using single-capacitor pulse width to analog converter based DAC

This work presents a SAR ADC using single-capacitor pulse width to analog converter based DAC. In the proposed scheme, the single-capacitor DAC is realized by partially charging or discharging the sampling capacitor with a DC reference current. The charge and discharge time is determined by the pulse width of the control signal. As a result, a SAR ADC can be realized by using a single-capacitor, current source, current mirror, comparator, and control logic, which can significantly reduce the circuit area and simplifies the switch control scheme compared to conventional SAR ADCs using capacitor DACs. A 6-bit SAR ADC is designed using CMOS 0.35μm technology where the operation is verified through circuit level simulations.

A power-efficient polyphase sharpened CIC filter for sigma-delta ADCs

This paper presents a power-efficient poly-phase sharpened CIC filter for sigma-delta ADCs. In this scheme, by using a cascade of CIC filter and SCIC filter with proper optimization of the two-stage decimation structure, the power consumption can be considerably reduced compared to conventional SCIC filter architectures. Furthermore, poly-phase implementations for both the CIC and SCIC filter sections are used to further reduce the power. The proposed filter is designed with CMOS 1µm technology, where the lowest power consumption is achieved among similar filter architectures.

A temperature and process insensitive CMOS reference current generator

This work presents a temperature and process insensitive CMOS transistor only reference current generator. In the proposed scheme, the passive resistor used in the CMOS Widlar current source is replaced with a transistor resistor where the gate voltage is controlled so that the output current is insensitive to temperature variation. Furthermore, to maintain the temperature insensitivity under process variations, the transistor resistor gate bias circuits optimized for nominal, strong and weak process corners are built on-chip. The proposed reference current generator is designed using 0.5 μm CMOS SOI technology, where the operation is verified through circuit level simulations under nine different process corners. The 20 μA reference current shows a temperature coefficient of 39 ppm/°C within the temperature range of 25°C ~ 125°C for the nominal process corner.