Kyeong-ryeol Bae

A Rectification Hardware Architecture for an Adaptive Multiple-Baseline Stereo Vision System

In this paper, we propose a new rectification hardware architecture that is suitable for an adaptive multiple-baseline stereo vision system. The adaptive multiple-baseline stereo vision system can obtain precise distance information compared with the fixed-baseline stereo vision system. To reduce the computation overhead of the stereo matching, the rectification is an essential step in the stereo vision system. However, the conventional rectification hardware architectures are designed for the fixed-baseline stereo vision system. Also, previously proposed the lookup table (LUT) based rectification hardware architectures are not suitable for the adaptive multiple-baseline stereo vision system. This is because these require large memory resources as the number of baseline increases. The experimental results show that the proposed hardware architecture does not need memory resources and also only few additional hardware resources are required as the number of the baseline increases as compared with the LUT-based rectification hardware.

Design and analysis of 3D IC-based low power stereo matching processors

This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.

An accurate and cost-effective stereo matching algorithm and processor for real-time embedded multimedia systems

Stereo matching is a vision technique for finding three-dimensional (3D) distance information in various multimedia applications by calculating pixel disparities between the matching points of a stereo image pair captured from a stereo camera. The most important considerations in stereo matching are highly accurate results and real-time performance. Thus, this paper proposes an accurate stereo matching algorithm that uses both a census transform algorithm and the sum of absolute differences algorithm in a complementary manner and its real-time hardware architecture. In addition, the proposed algorithm uses a vertical census transform with cost aggregation (VCTCA) to reduce hardware costs while maintaining high matching accuracy. We model the proposed algorithm using C language and verify it in several environments. Using a hardware description language, we implement the proposed hardware architecture and verify it on a field-programmable gate array-based platform to confirm the cost and performance of the hardware. The experimental results show that the proposed algorithm using the VCTCA produces accurate 3D distance information in real environments and reduces the hardware complexity. Thus, the algorithm and its hardware architecture are suitable for real-time embedded multimedia systems.

A census-based stereo matching algorithm with multiple sparse windows

Stereo matching is one of the most active research areas in intelligent vehicle technology. In order to apply the stereo matching to intelligent vehicles, it must generate high-accuracy three-dimensional information in real time. For real-time stereo matching, this paper proposes a sparse multi-window method which not only gives robustness to noise but also reduces hardware cost with high matching accuracy. This is achieved by reusing the result of overlapped operations between adjacent windows. The experimental results show that the proposed method can reduce the hardware complexity of stereo matching processors with higher accuracy compared with the conventional window method.

A hardware architecture based on the NCC algorithm for fast disparity estimation in 3D shape measurement systems

This paper proposes an efficient hardware architecture to estimate disparities between 2D images for generating 3D depth images in a stereo vision system. Stereo matching methods are classified into global and local methods. The local matching method uses the cost functions based on pixel windows such as SAD(sum of absolute difference), SSD(sum of squared difference) and NCC(normalized cross correlation). The NCC-based cost function is less susceptible to differences in noise and lighting condition between left and right images than the subtraction-based functions such as SAD and SSD, and for this reason, the NCC is preferred to the other functions. However, software-based implementations are not adequate for the NCC-based real-time stereo matching, due to its numerous complex operations. Therefore, we propose a fast pipelined hardware architecture suitable for real-time operations of the NCC function. By adopting a block-based box-filtering scheme to perform NCC operations in parallel, the proposed architecture improves processing speed compared with the previous researches. In this architecture, it takes almost the same number of cycles to process all the pixels, irrespective of the window size. Also, the simulation results show that its disparity estimation has low error rate.

An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing

This paper presents a new interworking architecture for a network processor (NP) that is able to process packets from OSI layer 2 (L2) to layer 7 (L7) by combining a conventional NP with a general-purpose processor (GP). In general, most commercially available NPs could not afford to support a variety of network services. This is mainly because the conventional NPs are not able to process L7 packets. Thus, one of the most important requirements for the state-of-the-art NP is the ability to process packets of L2 to L7. To process L7 packets efficiently through both the conventional NP and GP, the proposed interworking architecture uses a deep packet inspector (DPI) and it controls the packet processing flow depending on the OSI layers of packets. Experimental results show that the proposed interworking architecture is not only able to process packets of L2 to L7 but also increase the throughput and load balance of the packet processing in the NP without large hardware overhead when compared with the conventional interworking architecture.

A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000

In this paper, we propose a fully parallel, high-speed bit-plane coding (BPC) hardware architecture for the embedded block coding with optimized truncation (EBCOT) module in JPEG 2000. The BPC is the most complicated and critical part in design and implementation of the EBCOT. In addition, the BPC consumes most of the computation time in the EBCOT. Thus, a high-speed BPC hardware architecutre is strongly required for the real-time high-resolustion JPEG 2000 systems. To increase BPC throughput, the proposed hardware architecture performs BPC coding in all the bit planes in parallel through the proposed significance look-ahead methods. Experimental results show that the proposed architecture increases BPC throughput twice when compared with the previously proposed BPC architectures.