Kyoichiro Asayama

A stacked split word-line (SSW) cell for low-voltage operation, large capacity, high speed SRAMs

Stacked Split Word-Line cell technology suitable for low voltage operation, large capacity and high speed SRAMs has been proposed. Two pull-down transistors and two access transistors are fabricated employing two separate gate formations. A pair of split word-lines is stacked over pull-down transistors. That permits large cell ratio in small cell area and independent optimization of pull-down and access transistors. Threshold voltage of access transistors is lowered to improve cell stability. Top gate thin film polysilicon transistor and Vcc plate are used to make cell node capacitor and improve soft error immunity. This technology is applied to a fast 16M bit SRAM and enabled a 7.16 /spl mu/m/sup 2/ cell area in relaxed 0.4 /spl mu/m layout rule utilizing conventional i-line stepper without phase-shift masks.<<ETX>>

Bipolar CMOS-merged technology for a high-speed 1-Mbit DRAM

A novel high-performance bipolar-CMOS (complementary metal oxide semiconductor) merged technology for a 1-Mb DRAM (dynamic random access memory) is proposed. A memory cell having a twenty-times-higher soft-error immunity (as compared to the conventional device) in its bit-line mode and a bipolar transistor having a high-drive ability (f/sub T/=5.2 GHz at I/sub c/=1.2 mA) can be realized. The fabrication process is fully compatible with the conventional CMOS DRAM and involves only three additional masking steps. An experimental 1-Mb BiCMOS (bipolar CMOS) DRAM was fabricated using this technology, with a typical access time of 32 ns. >

Physical and chemical analytical instruments far failure analyses in Gbit devices

The current status and future trend of analytical instruments are discussed. Analytical instruments for failure analyses in sub-1/4 micron dimensions or less, require high spatial resolution and sensitivity at atomic levels. Using new analytical instruments, such as the nano-prober for electrical characteristics inspection in actual circuits, TEM-EELS for chemical bond analysis of nanometer area and GDS for precise composition analysis, it was found that a SiO/sub 2/ or TiO/sub x/ film formed by water from titanic acid (TiO/sub x/H/sub 2/O) produced with titan, water and chlorine, was a cause of high resistivity for a contact (CVD-W/CVD=TiN/Ti/Si) in sub-1/4 micron devices.