Hiroyuki Miyazawa

A 23-ns 1-Mb BiCMOS DRAM

A 1-Mb BiCMOS DRAM having a 23-ns access time is described. The DRAM uses a direct sensing technique and a nonaddress-multiplexing configuration. This technique combines the NMOS differential circuit on each pair of data lines with a common highly sensitive bipolar circuit. The resulting chip has been verified to have high-speed characteristics while maintaining a wide operating margin and a relatively small chip size of 62.2 mm/sup 2/, in spite of a 1.3- mu m lithography level. >

A 23ns 1Mbit BiCMOS DRAM

I -_JLd Lioduction Bit density oi DRAMs has continued to be improved by a factor of four times every three years. In contrast with these remarkable improvemenls in bit densitv, improvements in access and cycle times of DRAMs available in the market are insufficient for higher performance applications. For improving DRAM speed with reasonable process complexity, a 1.3ßm 1Mbit BiCMOS DRAM has been reported (I). However, performance of the previous DRAM is insufficient, although BiCMOS technology was verified as having advantages for improving speed, power dissipation and soft error rate (2)(3). In this paper, a 23ns 1.3 fi m 1Mbit BiCMOS DRAM, suitable for imss production, is described. First, high-speed sensing circuit techniques combined with a non

A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array

A system integrated LSI chip (SLSI) that contains eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array, for a graphics application system is described. To implement the SLSI on a silicon chip, three key techniques have been developed: (1) system redundancy for defect relief; (2) chip configuration and fabrication with blade masking to achieve a hybrid 38.16*50.4-mm/sup 2/ chip; and (3) large-capability and high-reliability 324-pin 54*86-mm/sup 2/ plastic pin grid array package. Using a system redundancy technique, a 60% yield for the SLSI is achieved with a 40% yield for the DRAM itself. That is twice the 30% yield of the conventional repair scheme. Access times are 65 ns for the DRAM and 14 ns for the SRAM with a 3.9-W chip power dissipation. >