Kyoji Yamashita

1/ f -Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation

SUMMARY A systematic experimental and modeling study is reported, which characterizes the low-frequency noise spectrum of 100 nmMOSFETs accurately. Two kinds of measured spectra are observed: 1/f and non-1/f spectra. The non-1/f spectrum is analysed by forward and backward measurements with exchanged source and drain, and shown to be due to a randomly distributed inhomogeneity of the trap density along the channel and within the gate oxide. By averaging the spectra of identical MOSFETs on a wafer the measured non-1/f noise spectra reduce to a 1/f characteristics. On the basis of these measurement data a noise model for circuit simulation is developed, which reproduces the low-frequency noise spectrum with a single model parameter for all gate lengths and under any bias conditions.

Mask defect inspection method by database comparison with 0.25-0.35 μm sensitivity

Photomasks used in the fabrication of ultra-LSI (ULSI) circuits must be inspected for defects. For 256 Mbit dynamic random access read write memory (DRAM), it is necessary to inspect defects as small as 0.15 µ m. Moreover, inspection of defects of phase-shift masks is becoming an important task of an inspection system. This paper describes an automated mask inspection system (MC-100) based on die-to-database comparison, and a defect inspection method with 0.15 µ m sensitivity for edge and pindot defects. System configuration and the defect inspection method are discussed in detail, including the difficulties of defect detection in an attenuated phase-shift mask.

Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

A Test Structure for Two-Dimensional Analysis of MOSFETs by Hot-Carrier-Induced Photoemission

A test structure and method for two-dimensional analysis of fabrication process and reliability of MOSFET using a photoemission microscope are presented. Arrays of 20/spl times/10(=200) MOSFETs were successfully measured at a time and evaluated the fluctuation of their characteristics. The fluctuation of hot-carrier-induced photoemission intensity was larger as gate length becomes smaller. Although the intensity fluctuation of photoemission in the same MOSFET was within small range, the fluctuation all over the MOSFET array was relatively large and independent of the position in the array.

A New Inspection Method for Phase-Shift Mask (PSM) on Deep-UV Inspection Light Source

As the mask pattern becomes smaller and more complex, the demand for a highly precise mask inspection system with high detection sensitivity and few false defects increases. In regard to inspection systems using a deep-UV wavelength, some issues have been encountered concerning inspection of an ArF-halftone (ArF-HT) mask, which is now entering practically used. In this paper, we report the defect detection sensitivity of Cr and KrF-HT masks, and discuss the issues concerning ArF-HT mask inspection and countermeasures to deal with them.

Variable sensitivity detection (VSD) technology for screening SRAF nuisance defects

This paper describes a novel technology Variable Sensitivity Detection (VSD) for de-sensing SRAF nuisance defects in a mask inspection system. The point of our approach is to search the nearest thin-line to each defect candidate and estimate the line-width with transmitted and reflected images. The dependence of transmitted and reflected image contract on line-width is calculated with a rigorous model. This technology de-senses lineend shortening and edge roughness of SRAF patterns without compromising sensitivity to main features. Total counts of SRAF nuisance detection were drastically reduced. The VSD technology was implemented to a platform of Nuflare NPI-5000PLUS.

Gray map reference pattern generator of a die-to-database mask inspection system for 256-Mb and 1-Gb DRAMs

This paper describes a reference data generation method applied to a newly developed photolithographic mask inspection system, the MC-2000, for 256 Mbit and 1 Gbit DRAMs. The MC-2000, which utilizes i-line wavelength optics, is designed to have a defect detection capability as fine as 0.2 micrometers . A new reference data generation method employing a gray map pattern is effective for system performance in terms of accuracy of the map pattern and speed of the map data handling. Notable features of the gray map pattern generation method are simple algorithm and ease of hardware implementation. Corner pattern rounding circuit, re-sizing circuit, and reference data calculation have been developed together and are described, too. The proposed method was evaluated and an example of the detection of 0.2 micrometers defect is reported.

Automatic photomask defect classification method

This paper describes a new image-processing algorithm for classifying photomask defects as pindots or contamination as a step toward automated inspection equipment for the one-micron generation. To detect contamination on quartz, our method extracts the gradient of the transmitted image within the dark region of reflected image. Contamination on the opaque membrane can also be detected by using the same method but with the transmitted image and reflected image mutually transposed. Standard particles of 0.3 to 0.5 micron can be detected with particles on quartz and particles on opaque membrane separated.

Design for nanoimprint lithography: hot spot modification through total NIL process simulation

Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. Layout and process dependent hotspots become a significant issue for application in smaller pattern size device and, design for manufacturing (DFM) flow comprising imprint process has to be prepared. Focusing on resist drop arrangement method as a process margin expansion knob, simulated non-fill defect is compared with experimental result. Finally, drop arrangement-related hot-spot extraction/modification flow utilizing total NIL simulation is proposed.

RLT uniformity improvement utilizing multi-scale NIL process simulation

Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. To apply smaller pattern size device, layout dependent hotspots becomes a significant issue, so design for manufacturing (DFM) flow considering imprint process has to be prepared. In this paper, focused on fine resist spread, RLT (Residual Layer Thickness) uniformity improvement utilizing simulation is demonstrated and resist drop compliance check flow is proposed