Hans Jürgen Mattausch

Status and trends of power semiconductor device models for circuit simulation

The current status of research in the field of power semiconductor device models is reviewed. For this purpose, the basic modeling problems and research issues, which have to be overcome in this field, are discussed. Some new and quite promising modeling concepts have been proposed, which are compared with more traditional ways of achieving an efficient tradeoff between the necessary accuracy, required simulation speed, and feasibility of parameter determination. From this comparison, a prediction of the future evolution of circuit simulation models for power semiconductor devices naturally emerges. Many of the different concepts are expected to survive only in an application niche, where their specific points of strength are important. However, three modeling concepts have already been proven to be successfully applicable to the complete spectrum of power semiconductor devices and have their strength for different grades of complexity of the power circuit. A revolutionary development from anticipated or long-due breakthroughs is on the other hand not expected in the foreseeable future.

HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximations without any computer run-time penalty. It is further demonstrated that excellent model accuracy for higher-order phenomena, which is a prerequisite for accurate RF circuit simulation, is achieved by HiSIM without any new model parameters in addition to those for describing the current-voltage characteristics

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

A precise model for the transient characteristics of power diodes

A power diode model for circuit simulations is described. All important phenomena like transient behavior, temperature dependence, emitter recombination, mobile charge carriers in depletion layer, carrier multiplication, and self-heating are included. Comparisons between simulations and measurements show less than 10% deviation of current and voltage over the temperature range of 25 degrees C-125 degrees C.<<ETX>>

Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance

An associative-memory architecture for a fully parallel minimum Hamming distance search is proposed, which uses digital circuitry for bit comparison and fast analog circuitry for word comparison as well as winner-take-all (WTA) functionality. Following this original approach allows compact and high-performance integration in conventional CMOS technology. First, static encoding of word-comparison results as a current-sink capability reduces word-comparison circuitry to the theoretical minimum, namely, one transistor per bit and one signal line per word. Second, a new WTA principle, which we call self-adapting winner line-up amplification (WLA), regulates the winner row output automatically into the narrow maximum-gain region of a distance amplifier. Third, winner search circuit complexity scales linear with reference-word number and not quadratic as inevitable for digital approaches. Due to static distance encoding and WLA regulation, transient noise and fabrication process variations are largely tolerated. Only relative chip-internal transistor-parameter variations, creating effective mismatch of matched transistors, limit winner search result correctness. Practical feasibility is verified.

Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects

The reported circuit simulation model Hiroshima University semiconductor technology academic research center IGFET model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI-MOSFET is based on a complete surface-potential description. Not only the surface potential in the MOSFET channel, but also the potentials at both surfaces of the buried oxide are solved iteratively, which allows including of all relevant device features of the SOI-MOSFET explicitly and in a physically correct way. In particular, an additional parasitic electric field, induced by the surface-potential distribution at the buried oxide, has to be included for accurate modeling of the short-channel effects. The total iteration time for surface potential calculation with HiSIM-SOI is under most bias conditions only a factor 2.0 (up to a factor 3.0 for some bias conditions) longer than for the bulk-MOSFET HiSIM model, where just the channel surface potential is involved. It is verified that HiSIM-SOI reproduces measured current-voltage (I-V) and 1/f noise characteristics of a 250-nm fully depleted SOI technology in the complete operating range with an average error of 1% and 15%, respectively. Stable convergence of HiSIM-SOI in the circuit simulation is confirmed

The physics and modeling of MOSFETS : surface-potential model HiSIM

Semiconductor Device Physics Basic Compact Surface-Potential Model of the MOSFET Advanced MOSFET Phenomena Modeling Capacitances Noise Models Non-Quasi-Static (NQS) Model Leakage Currents Source/Bulk and Drain/Bulk Diode Models Source/Drain Resistances Effects of the Source/Drain Diffusion Length for Shallow Trench Isolation (STI) Technologies Summary of Model Equations Exclusion of Modeled Effects and Model Flags.

A Carrier-Transit-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application to Harmonic Distortion Analysis

In this paper, a compact model of nonquasi-static (NQS) carrier-transport effects in MOSFETs is reported, which takes into account the carrier-response delay to form the channel. The NQS model, as implemented in the surface-potential-based MOSFET Hiroshima University STARC IGFET model, is verified to predict the correct transient terminal currents and to achieve a stable circuit simulation. Simulation results show that the NQS model can even reduce the circuit simulation time in some cases due to the elimination of unphysical overshoot peaks normally calculated by a QS-model. An average additional computational cost of only 3% is demonstrated for common test circuits. Furthermore, harmonic distortion characteristics are investigated using the developed NQS model. While the distortion characteristics at low drain bias and low switching frequency are determined mainly by carrier mobility, distortion characteristics at high frequency are found to be strongly influenced by channel charging/discharging

HiSIM-HV: A Compact Model for Simulation of High-Voltage MOSFET Circuits

The completely surface-potential-based MOSFET model HiSIM-HV for high-voltage applications of up to several hundred volts is reviewed, and recently developed new model capabilities are presented. HiSIM-HV enables a consistent evaluation of current and capacitance characteristics for symmetric and asymmetric high-voltage MOSFETs due to a consistent description of the potential distribution across the MOSFET channel as well as the resistive drift regions. The anomalous features, often observed in the capacitances, are explained by large potential drops in the drift regions. Accurate modeling of the overlap region between the gate and drift region is also demonstrated. Different device features based on different device structures are well explained by the geometrical differences.

A scalable massively parallel processor for real-time image processing

This paper describes a high performance scalable massively parallel single-instruction multiple-data (SIMD) processor and power/area efficient real-time image processing. The SIMD processor combines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high performance of 191 GOPS, a high power efficiency of 310 GOPS/W, and a high area efficiency of 31.6 GOPS/mm2 . The applied pipeline architecture is optimized to reduce the number of controller overhead cycles so that the SIMD parallel processing unit can be utilized during up to 99% of the operating time of typical application programs. The processor can be also optimized for low cost, low power, and high performance multimedia system-on-a-chip (SoC) solutions. A combination of custom and automated implementation techniques enables scalability in the number of PEs. The processor has two operating modes, a normal frequency (NF) mode for higher power efficiency and a double frequency (DF) mode for higher performance. The combination of high area efficiency, high power efficiency, high performance, and the flexibility of the SIMD processor described in this paper expands the application of real-time image processing technology to a variety of electronic devices.