Kyoungwoo Lee

Mitigating soft error failures for multimedia applications by selective data protection

With advances in process technology, soft errors(SE)are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft errors. Although Error Correction Code based mechanisms protect the data in caches, they have high performance and power overheads. Since multimedia applications are increasingly being used in mission-critical embedded systems where both reliability and energy are a major concern, there is a de?nite need to improve reliability in embedded systems, without too much energy overhead. We observe that while a soft error in multimedia data may only result in a minor loss in QoS, a soft error in avariable that controls the execution ?ow of the program may be fatal. Consequently, we propose to partition the data space into failure critical and failure non-critical data, and provide a high-degree of soft error protection only to the failure critical data in Horizontally Partitioned Caches. Experimental results demonstrate that our selective data protection can achieve the failure rate close to that of a soft error protected cache system, while retaining the performance and energy consumption similar to those of a traditional cache system, with some degradation in QoS. For example, for conventional con?guration as in IntelXScale, our approach achieves the same failure rate, while improving performance by 28% and reducing energy consumption by 29%in comparison with a soft error protected cache.

A cross-layer approach for power-performance optimization in distributed mobile systems

The next generation of mobile systems with multimedia processing capabilities and wireless connectivity will be increasingly deployed in highly dynamic and distributed environments for multimedia playback and delivery (e.g. video streaming, multimedia conferencing). The challenge is to meet the heavy resource demands of multimedia applications under the stringent energy, computational, and bandwidth constraints of mobile systems, while constantly adapting to the global state changes of the distributed environment. In this paper, we present our initiatives under the FORGE framework to address the issue of delivering high quality multimedia content in mobile environments. In order to cope with the resource intensive nature of multimedia applications and dynamically changing global state (e.g. node mobility, network congestion), an end-to-end approach to QoS aware power optimization is required. We present a framework for coordinating energy optimizing strategies across various layers of system implementation and functionality and discuss techniques that can be employed to achieve energy gains for mobile multimedia systems.

Multiple-robot drug delivery strategy through coordinated teams of microswimmers

Untethered robotic microswimmers are very promising to significantly improve various types of minimally invasive surgeries by offering high accuracy at extremely small scales. A prime example is drug delivery, for which a large number of microswimmers is required to deliver sufficient dosages to target sites. For this reason, the controllability of groups of microswimmers is essential. In this paper, we demonstrate simultaneous control of multiple geometrically similar but magnetically different microswimmers using a single global rotating magnetic field. By exploiting the differences in their magnetic properties, we triggered different swimming behaviors from the microswimmers by controlling the frequency and the strength of the global field, for example, one swim and the other does not while exposed to the same control input. Our results show that the balance between the applied magnetic torque and the hydrodynamic torque can be exploited for simultaneous control of two microswimmers to swim in opposite directions, with different velocities, and with similar velocities. This work will serve to establish important concepts for future developments of control systems to manipulate multiple magnetically actuated microswimmers and a step towards using swarms of microswimmers as viable workforces for complex operations.

Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach

Increasing exponentially with each technology generation, hardware-induced soft errors pose a significant threat for the reliability of mobile multimedia devices. Since traditional hardware error protection techniques incur significant power and performance overheads, this paper proposes a cooperative cross-layer approach that exploits existing error control schemes at the application layer to mitigate the impact of hardware defects. Specifically, we propose error detection codes in hardware, drop and forward recovery in middleware, and error-resilient video encoding at the application level to effectively and efficiently combat soft errors with minimal overheads. Experimental evaluation on standard test video streams demonstrates that our cooperative error-aware method for video encoding improves performance by 60% and energy consumption by 58% with even better reliability at the cost of only 3% quality degradation on average, as compared to an error correction code based hardware protection technique. Combining intelligent schemes to select a recovery mechanism can guide system designers to trade off multiple constraints such as performance, power, reliability, and QoS.

Home networking digital TV based on LnCP

This paper presents the home networking protocol, LnCP which has been developed to connect home appliances. Then a digital TV that can communicate with other appliances using LnCP is introduced.

Efficient parity placement schemes for tolerating up to two disk failures in disk arrays

Abstract In order to achieve high reliability in disk array systems, two new schemes using dual parity placement, called DH1 (diagonal–horizontal) and DH2 schemes, are presented. Both DH schemes can tolerate up to two disk failures by using two types of parity information placed in the diagonal and the horizontal directions, respectively, in a matrix of disk partitions. DH1 scheme can reduce the occurrences of the bottleneck problem significantly because the parity blocks are evenly distributed throughout the disk array. DH2 scheme uses one more disk than DH1 scheme in order to store the horizontal parities, while the diagonal parities are placed in the same way as in DH1 scheme with a minor change. Even though both DH schemes use almost optimal disk space for storing the redundant information, the encoding algorithms for them are quite simple and efficient. Moreover, both DH schemes can recover rapidly from any two disk failures.

Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications

With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimedia applications, not all data require the same amount of protection from soft errors, we propose a partially protected cache (PPC) architecture, in which there are two caches, one protected and the other unprotected at the same level of memory hierarchy. We demonstrate that as compared to the existing unprotected cache architectures, PPC architectures can provide 47 times reduction in failure rate, at only 1% runtime and 3% power overheads. In addition, the failure rate reduction obtained by PPCs is very sensitive to the PPC cache configuration. Therefore, this observation provides an opportunity for further improvement of the solution by correctly parameterizing the PPC configurations. Consequently, we develop design space exploration (DSE) strategies to discover the best PPC configuration. Our DSE technique can reduce the exploration time by more than six times as compared to an exhaustive approach.

Performance improvement in ZigBee-based home networks with coexisting WLANs

In recent years, a large diversity of network-enabled devices have been widely prevalent in home environment. With the prevalence of such devices, wireless home networks enable monitoring and control applications for home user comfort and efficient home management. In the home network, alarm signals must be delivered in real-time to the residents or to the emergency services and some home control applications require the response time to be on the order of a few hundred milliseconds for optimal user experience. Most recently, ZigBee has emerged as one of the most promising technologies for wireless home networking because it is targeted at applications that require a low data rate and long battery life, which are also the features of home network applications. However, its usage in close proximity to Wireless Local Area Networks (WLANs) introduces coexistence problems, resulting in failing to fulfil the response time required by the home control applications. To overcome this problem, we propose to control the WLAN traffic when there exist ongoing ZigBee transmissions and the maximum tolerable delay is not met due to the WLAN interference. We aim to guarantee that the delay experienced by ZigBee sensors (especially, for alarm signals) does not exceed the maximum tolerable delay, while maintaining as high throughput as possible in the WLANs. The simulation results demonstrate that our proposed algorithm can enhance the delay performance of ZigBee networks by mitigating the effect of WLAN interference and improve the throughput in the WLANs.

Error-Exploiting Video Encoder to Extend Energy/QoS Tradeoffs for Mobile Embedded Systems

Energy/QoS provisioning is a challenging task for video applications in power-constrained mobile embedded systems. Many error-resilient video encodings allow us to exploit errors and generate a range of acceptable tradeoff spaces by controlling the amount of errors in the system. This expanded tradeoff space allows system designers to comparatively evaluate different operating points with varying QoS and energy consumption by aggressively exploiting error-resilience attributes, and can potentially result in significant energy savings. Specifically, we propose an error-aware video encoding technique that intentionally injects errors (drops frames) while ensuring QoS in accordance with error-resilience. The novelty of our approach is in active exploitation of errorsto vary the operating conditions for further optimization of system aspects. Our experiments show that our error-exploiting video encoding can reduce the energy consumption for an encoding device by 37% in video conferencing over a wireless network, without video quality degradation, compared to a standard video encoding technique for a test video stream. Furthermore, we present the adaptivity of our approach by incorporating the feedback from the decoding side to achieve the QoS requirement under dynamic network status.

UnSync-CMP: Multicore CMP Architecture for Energy-Efficient Soft-Error Reliability

Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are only consequences of the inevitable advancement in processor technology, the industry has been forced to improve reliability on general purpose chip multiprocessors (CMPs). With the availability of increased hardware resources, redundancy-based techniques are the most promising methods to eradicate soft-error failures in CMP systems. In this work, we propose a novel customizable and redundant CMP architecture (UnSync) that utilizes hardware-based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error-free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. The inherent nature of our architecture framework supports customization of the redundancy, and thereby provides means to achieve possible performance-reliability tradeoffs in many-core systems. We provide a redundancy-based soft-error resilient CMP architecture for both write-through and write-back cache configurations. We design a detailed RTL model of our UnSync architecture and perform hardware synthesis to compare the hardware (power/area) overheads incurred. We compare the same with those of the Reunion technique, a state-of-the-art redundant multicore architecture. We also perform cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture. Experimental results show that, our UnSync architecture reduces power consumption by 34.5 percent and improves performance by up to 20 percent with 13.3 percent less area overhead, when compared to the Reunion architecture for the same level of reliability achieved.