Yohan Ko

Guidelines to design parity protected write-back L1 data cache

Several decades of technology scaling has brought the challenge of soft errors to modern computing systems, and caches are most susceptible to soft errors. While it is straightforward to protect L2 and other lower level caches using error correcting coding (ECC), protecting the L1 data caches poses a challenge. Parity-based protection of L1 data cache is a more power-efficient alternative, however, some questions still linger - How effective is parity protection for caches? How can we design a parity-based L1 data cache so as to maximize the protection achieved? The goal of this paper is to perform a quantitative evaluation of the protection afforded by various parity-protected cache design alternatives, and formulate guidelines for the design of power-efficient and reliable L1 data caches. Towards this goal, this paper develops an algorithm to accurately model the vulnerability of data in caches, in the presence of various configurations of parity protection, and validate it against extensive fault injection campaigns. We find that, (i) checking parity at reads only (and not at writes) provides 11% more protection with 30% lesser power overheads as compared to that at both reads and writes; and (ii) when implementing parity at the word-level granularity for 53% improved protection as compared to block-level parity implementation, the dirty-bits in the cache should also be implemented at the same granularity, otherwise, there is no improvement in protection. We find several popular commercial processors - even the ones specifically designed for reliability - not following these design guidelines, and resulting in sub-optimial designs.

Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures

Soft errors are becoming a critical concern in embedded system designs. Code duplication techniques have been proposed to increase the reliability in multi-issue embedded systems such as VLIW by exploiting empty slots for duplicated instructions. However, they increase code size, another important concern, and ignore vulnerability differences in instructions, causing unnecessary or inefficient protection when selecting instructions to be duplicated under constraints. In this article, we propose a compiler-assisted dynamic code duplication method to minimize the code size overhead, and present vulnerability-aware duplication algorithms to maximize the effectiveness of instruction duplication with least overheads for VLIW architecture. Our experimental results with SoarGen and Synopsys simulation environments demonstrate that our proposals can reduce the code size by up to 40% and detect more soft errors by up to 82% via fault injection experiments over benchmarks from DSPstone and Livermore Loops as compared to the previously proposed instruction duplication technique.

Selective validations for efficient protections on Coarse-Grained Reconfigurable Architectures

Coarse-Grained Reconfigurable Architectures or CGRAs are drawing significant attention since they promise both performance with parallelism and flexibility with reconfiguration. Soft errors or transient faults are becoming a serious design concern in embedded systems including CGRAs since soft error rate is increasing exponentially as technology scaling. A recently proposed software-based technique with TMR (Triple Modular Redundancy) implemented on CGRAs incurs extreme performance overhead mainly due to expensive voting mechanisms for outputs from triplication of every operation. In this paper, we propose selective validation mechanisms for efficient modular redundancy techniques in the datapaths on CGRAs. Our techniques selectively validate results at synchronous operations rather than every operation in order to reduce the expensive performance overhead from the validation mechanism. Our experimental results demonstrate that our selective validation based TMR technique can improve the performance by 38.3% on average over benchmarks as compared to the recently proposed software-based TMR technique with the full validation.

Collaborative classification for daily activity recognition with a smartwatch

Research of daily activity recognition has been extensively conducted in the field of ubiquitous computing. However, previous daily activity recognition schemes are either obtrusive or inaccurate since they use just special-purpose devices. In this paper, we propose the collaborative classification for recognizing daily activities with a smartwatch. We exploit a single off-the-shelf smartwatch to distinguish 5 different daily activities such as eating, vacuuming, sleeping, showering, and TV watching. More precisely, we conduct experiments for collecting sensor data from accelerometer and acoustic sensor which are embedded in a smartwatch. However, the simple combination of the raw acceleration and acoustic data does not deliver accurate recognition accuracy. In order to achieve high accuracy, we propose a collaborative classification algorithm which integrates sensor data and ground-truth label for improving recognition accuracy by constructing a mapping table. We evaluate accuracies using single-sensor based approach, multi-sensor based approach, and our collaborative classification approach. The results from activity recognition for about 20 hours data collected by subjects show reliable accuracies for all 5 activities, and the overall accuracy of our collaborative approach is about 91.5%. Experimental results reveal that our approach improves the recall rate of each activity by up to 21.5% as compared to that of the simply combined multi-sensor based approach.

Software-Based Selective Validation Techniques for Robust CGRAs Against Soft Errors

Coarse-Grained Reconfigurable Architectures (CGRAs) are drawing significant attention since they promise both performances with parallelism and flexibility with reconfiguration. Soft errors (or transient faults) are becoming a serious design concern in embedded systems including CGRAs since the soft error rate is increasing exponentially as technology is scaling. A recently proposed software-based technique with TMR (Triple Modular Redundancy) implemented on CGRAs incurs extreme overheads in terms of runtime and energy consumption mainly due to expensive voting mechanisms for the outputs from the triplication of every operation. In this article, we propose selective validation mechanisms for efficient modular redundancy techniques in the datapaths on CGRAs. Our techniques selectively validate the results at synchronous operations rather than every operation in order to reduce the expensive performance overhead from the validation mechanism. We also present an optimization technique to further improve the runtime and the energy consumption by minimizing synchronous operations where a validating mechanism needs to be applied. Our experimental results demonstrate that our selective validation-based TMR technique with our optimization on CGRAs can improve the runtime by 41.0% and the energy consumption by 26.2% on average over benchmarks as compared to the recently proposed software-based TMR technique with the full validation.

Enhanced indoor localization in home environments using appearance frequency information

Recognizing the location of an individual in a home environment is crucial in order to enable various context-aware home applications such as elderly health monitoring and in home appliance automation. However, due to the limited number of dedicated Wi-Fi access points (APs), it is challenging to guarantee the reliable localization performance in a home environment by using the traditional Wi-Fi fingerprinting (WF) technique. In this paper, we propose a room-level localization system for the typical residential home environments which comprise of a living room, a kitchen, a bathroom, and a bedroom. Specifically, we make use of appearance frequency (AF) information of APs at each location in order to narrow down the number of candidate locations before performing the Wi-Fi Fingerprinting scheme. Our system improves the localization performance by up to 17.5 % (11.29 % on average) over that of the traditional WF-based approach which does not exploit AF information. We achieved the room-level positioning accuracy of 84.76% on the dataset of 6 home environments.

Protecting Caches from Soft Errors: A Microarchitect’s Perspective

Soft error is one of the most important design concerns in modern embedded systems with aggressive technology scaling. Among various microarchitectural components in a processor, cache is the most susceptible component to soft errors. Error detection and correction codes are common protection techniques for cache memory due to their design simplicity. In order to design effective protection techniques for caches, it is important to quantitatively estimate the susceptibility of caches without and even with protections. At the architectural level, vulnerability is the metric to quantify the susceptibility of data in caches. However, existing tools and techniques calculate the vulnerability of data in caches through coarse-grained block-level estimation. Further, they ignore common cache protection techniques such as error detection and correction codes. In this article, we demonstrate that our word-level vulnerability estimation is accurate through intensive fault injection campaigns as compared to block-level one. Further, our extensive experiments over benchmark suites reveal several counter-intuitive and interesting results. Parity checking when performed over just reads provides reliable and power-efficient protection than that when performed over both reads and writes. On the other hand, checking error correcting codes only at reads alone can be vulnerable even for single-bit soft errors, while that at both reads and writes provides the perfect reliability.

Multi-level cache vulnerability estimation: The first step to protect memory

Cache is one of the most susceptible microarchitectural components against soft errors since cache memory not only takes up the majority of chip area but also is frequently accessed by other microarchitectural components. Several protection techniques have been proposed in order to improve the cache reliability. These cache protections can significantly affect the overall performance of the entire processor. Thus, it is extremely important to quantify the reliability of cache memory with and without protections in order to choose appropriate protection techniques. In this paper, we model the vulnerability estimation with considering generally used protection techniques, such as parity and error correction code, on multi-level cache memory. In common processors, level 1 and 2 caches are protected by parity and error correction code, respectively, but our experimental results reveal several interesting results. First off, parity protection for level 1 instruction cache can be good way to decrease the vulnerability, but it is inefficient for level 1 data cache. In special cases, parity protection for level 1 data cache can worsen the reliability as compared to unprotected cache. Secondly, parity protection for level 2 cache can decrease the vulnerability almost by half with the comparable overheads. For some benchmarks, parity protection for level 2 cache can be as reliable as error correcting code with much less overheads.