Kyung Joon Han

Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation

A highly scalable flash-based Field Programmable Gate Array (FPGA) technology has been achieved with Deep Trench Isolation (DTI). The DTI allows for a reduced cell size and enables Independent Pwell (IPW) operation. The IPW allows the Fowler-Nordheim (FN) Uniform Channel Program and Erase (UCPE) with less than plusmn10 V. Additionally, the IPW approach allows a greater flexibility in the array bias scheme reducing the gate disturb during programming and eliminating all Gate-Induced Drain Leakage (GIDL) conditions. Characterization of a FPGA cell and 0.5 Mbit array with 90 nm design rules is demonstrated with excellent electrical characteristics.

High performance 65nm 2T-embedded Flash memory for high reliability SOC applications

High speed array architecture and cell optimization in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) are investigated. It is important to optimize select gate (SG) channel length from 2T-eFlash test array when CG flash device width/length and SG length are pre-determined by other constraints. SG-punch through (PT) driven Gate Disturb (GD) and Gate Induced Drain Leakage current (GIDL) driven GD must be simultaneously studied to determine the optimum CG and SG spacing. For the applications requiring thick tunnel oxide (10nm) such as automotive products, the conductivities of the Sector Select Gate (SSG) device and Control Gate (CG) flash device are critical for read performance. A double SSG scheme per sector and common metal source line architecture were introduced. In this paper, we report our investigation results to optimize 2T eFlash cell design and array architecture to achieve high performance eFlash operation without sacrificing reliability within the constraint of embedding a flash process in the 65nm standard logic process.

Cycling impact on the Gm degradation and GIDL current of 65nm 2T-embedded Flash memory

Abnormal Gm degradation and GIDL current in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) is investigated. Severe charge trapping and de-trapping at the floating gate to junction overlap area lead to the endurance failure and cell current degradation. Control Gate (CG)-Select Gate (SG) Inter-junction trapping further degrades endurance and GIDL due to enhanced field and deeply depleted inter-junction. High temperature retention bake showed the charge relaxation and subsequent failure in the programmed cells. In this paper, we report both Gm and GIDL improvement of 2T eFlash memory with optimized gate-sidewall and extra thermal steps within the constraint of embedding flash process in the 65nm standard logic process.

Investigation of GIDL current Injection Disturb Mechanism in two-transistor-eNVM memory devices

A programming disturb mechanism in the uniform channel program and erase (UCPE) eFlash 2TC (two transistor cell) is investigated. High GIDL current from the SG (selected gate) on the selected row and unselected columns introduce additional gate disturbs in a high density eFlash product. It is observed that the 1TC eFlash without an SG configuration did not show the same mechanism. When the SG bias is optimized, the yield was maximized. The higher SG bias can result in an SG turn-on driven gate disturb and the lower SG bias can result in a GIDL driven disturb. The flash p-well bias was also optimized not only for program Vt window but GIDL current because of excessive substrate injection with a high junction field. These leaky bits can impact the overall yield. Optimizing the S/D junction profiles with Vt adjustment successfully suppressed the hot carrier injection induced disturb.

Investigation of substrate injection disturb mechanism in high density flash FPGA devices

A programming disturb mechanism in the uniform channel program and erase (UCPE) flash FPGA cell is investigated. High junction leakage from the inhibit bits on the selected row and unselected columns introduce additional gate disturb failures in a high density Flash FPGA product. It is observed that the total substrate current from the inhibit bits can induce the turn-on of a parasitic bipolar transistor from the neighboring transistor source/drain (S/D) through the substrate injection mechanism with a high field present. These leaky bits impact the overall yield and can later pose reliability concerns. Optimizing the S/D junction profiles with removal of Si defects successfully suppressed the injection induced disturb.

Highly Scalable Embedded Flash Memory With Deep Trench Isolation and Novel Buried Bitline Integration for the 90-nm Node and Beyond

In this paper, we embedded a Flash memory cell with 90-nm ground-rules in a high-performance CMOS logic process. A novel deep trench isolation (DTI) module enables an isolated p-well (IPW) bias scheme, leading to Flash with uniform channel program/erase by Fowler-Nordheim tunneling without gate induced drain leakage, a key feature for low-power portable electronics. The IPW concept leads to a compact cell design and a highly scalable high-voltage periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTI of each bitline (BL) from its neighboring BLs. We additionally present a buried BL (BBL) concept that links the source contacts of each individual BL via the IPW; thus, effectively eliminating one metal line per BL and reducing overall cell size. A conservative cell size shrink of about 40% can be achieved for a uniform channel program/erase-Flash cell with deep trench and BBL compared to a conventional 21F2cell.

Cycling induced degradation of a 65nm FPGA flash memory switch

We present a study of cycling induced degradation of a two transistor Flash memory cell with a shared floating gate. The cell directly serves as a configurable interconnection switch in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. By optimizing the poly re-oxidation, LDD implant and spacer module, the cell endurance is significantly improved at both the single cell and 1 Mbit test-array levels.

Single Bit Read Disturb failure mechanism and transistor size optimization for dual port SRAM bitcell in embedded NVM process SOC applications

We observed Single Bit Read Disturb failure in SRAM blocks with embedded Flash process. Such failures are not observed in pure logic process because pure logic process does not require additional thermal budget. In embedded Flash process, static Noise Margin (SNM) and leakage current degrades, causing more Single Bit Failure (SBF) at high VCC and/or high temperature. We optimized SRAM bitcells transistor size and improved the process leakage. We report the procedure for beta optimization and did standby leakage analysis, which points to the location electrically. After the process fix and bitcell beta increase, the SBF problem was resolved and the product became more reliable with more Static Noise Margin (SNM).