Patty Liu

High performance 65nm 2T-embedded Flash memory for high reliability SOC applications

High speed array architecture and cell optimization in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) are investigated. It is important to optimize select gate (SG) channel length from 2T-eFlash test array when CG flash device width/length and SG length are pre-determined by other constraints. SG-punch through (PT) driven Gate Disturb (GD) and Gate Induced Drain Leakage current (GIDL) driven GD must be simultaneously studied to determine the optimum CG and SG spacing. For the applications requiring thick tunnel oxide (10nm) such as automotive products, the conductivities of the Sector Select Gate (SSG) device and Control Gate (CG) flash device are critical for read performance. A double SSG scheme per sector and common metal source line architecture were introduced. In this paper, we report our investigation results to optimize 2T eFlash cell design and array architecture to achieve high performance eFlash operation without sacrificing reliability within the constraint of embedding a flash process in the 65nm standard logic process.

Cycling impact on the Gm degradation and GIDL current of 65nm 2T-embedded Flash memory

Abnormal Gm degradation and GIDL current in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) is investigated. Severe charge trapping and de-trapping at the floating gate to junction overlap area lead to the endurance failure and cell current degradation. Control Gate (CG)-Select Gate (SG) Inter-junction trapping further degrades endurance and GIDL due to enhanced field and deeply depleted inter-junction. High temperature retention bake showed the charge relaxation and subsequent failure in the programmed cells. In this paper, we report both Gm and GIDL improvement of 2T eFlash memory with optimized gate-sidewall and extra thermal steps within the constraint of embedding flash process in the 65nm standard logic process.

Investigation of GIDL current Injection Disturb Mechanism in two-transistor-eNVM memory devices

A programming disturb mechanism in the uniform channel program and erase (UCPE) eFlash 2TC (two transistor cell) is investigated. High GIDL current from the SG (selected gate) on the selected row and unselected columns introduce additional gate disturbs in a high density eFlash product. It is observed that the 1TC eFlash without an SG configuration did not show the same mechanism. When the SG bias is optimized, the yield was maximized. The higher SG bias can result in an SG turn-on driven gate disturb and the lower SG bias can result in a GIDL driven disturb. The flash p-well bias was also optimized not only for program Vt window but GIDL current because of excessive substrate injection with a high junction field. These leaky bits can impact the overall yield. Optimizing the S/D junction profiles with Vt adjustment successfully suppressed the hot carrier injection induced disturb.

NBTI life time of a high voltage PMOS FET

We present a study on NBTI life time for high voltage PMOS transistors. These devices are used in erasing and programming control circuits for a floating-gate flash based FPGA array fabricated with a 65nm embedded process. NBTI stress tests were performed with different gate biases and at different temperatures. Life time model parameters, such as voltage acceleration factor and activation energy, were obtained from the tested results. NBTI device life time was assessed against product requirements. A 50 times (50X) margin in life time was estimated for our baseline process, based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or completely depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases. To further improve NBTI lifetime margin against product requirement, LDD doping was increased and optimized. We are able to further improve HV PMOS device performance in this regard.

Voltage dependence and AC life time of PMOS HCI

In this work, HCI effect of PMOS FETs was studied. For a given drain bias, electron trapping is the dominant degradation mechanism for a gate bias close to 20% of the drain bias. A maximum gate current is seen under this bias condition. Hole trapping is dominant when the gate bias is equal to the drain bias where drain current is the maximum. Electron trapping enhances PMOS driving current or Idsat whereas hole trapping degrades Idsat. The effect of electron trapping and hole trapping cancel each other. As a result, life time is longer when two trapping mechanisms are involved compared with the life time with one trapping mechanism. In this study, device Idsat degradation was measured with different gate and drain biases in a DC mode. An AC stress is also performed in which gate/drain bias waveforms follow those of a typical switching inverter. Due to the above-mentioned cancelling effect, PMOS HCI AC life time is longer and the DC to AC conversion factor is much larger than conventionally used values. The effect of STI stress on HCI degradation is briefly studied. Layouts to minimize this effect are then proposed.

High voltage PMOS FET NBTI results and mechanism

We present a study on NBTI induced device degradation and mechanism for a high voltage PMOS FET. This device is used in erasing and programming a floating-gate Flash based FPGA array fabricated with a 65nm embedded process. NBTI induced device degradation has attracted a lot of attention and becomes the major limitation of logic PMOS reliability. Unlike logic devices which operate at high frequencies, program and erase of Flash cells are operated at a much lower frequency. Erase time is typically a few seconds per cycle, thus, in our study NBTI stress is done in a DC mode or a slow AC mode. In this case some device degradation gets recovered and a longer life time has been seen than logic applications. We have performed NBTI stress tests with different biases and at different temperatures. Life time model parameters, for example, voltage acceleration factor and Ea were obtained from the tested data. NBTI device life time was derived for erase conditions. A 50 times margin in life time was seen for our baseline process based on DC stress data. Longer AC life time is seen due to recovery of device degradation. This allows even more margin for the real operation. Interface trap and positive charge contributions to the observed Vt shift were separated from a recovery study. It is observed that interface traps can be recovered either partially or wholly depending on the recovery temperature. Positive charges can only be partially recovered at positive gate biases.

Annealing characteristics of radiation induced leakage in SOS MOSFETs

Recently, material procurement specifications for controlling and minimizing radiation induced leakage of integrated circuits in silicon-on-sapphire have been explored. It was demonstrated in some optimized SOS material fabrication conditions that a significant reduction in radiation induced leakage in SOS CMOS devices and circuits can be achieved at the price of somewhat reduced channel mobility and increased pre-radiation leakage levels. However, the understanding of reduction mechanisms in the radiation induced leakage is still lacking. In order to gain understanding of this phenomenon, the annealing behavior of the radiation induced leakage in SOS with new procurement specifications is investigated in this work. Based on the annealing results, a potential rad-hard method of low-temperature short-cycle annealing is proposed to cure radiation induced damage for further radiation hardening in space electronics applications.<<ETX>>

Program disturbs and process optimization in a 65 nm Flash FPGA

We present studies of an extrinsic program disturb mechanism in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. It is concluded that multiple positive charges are involved during disturb to explain the observed extrinsic behavior. Its failure rate was improved with tunnel oxidation process tuning and stronger pre-oxidation cleans.

Performance and reliability of a 65nm Flash based FPGA

We present a highly reliable Flash based FPGA fabricated with a 65nm embedded process. A very robust ON and OFF Vt window, over 8V, has been achieved with tight cell to cell distributions. 1k program/erase cycles have been performed and charge trap induced Vt window loss is less than 0.2V. Some initial Vt shift is seen at erase side after retention bake. The shift saturates after 24 hours and the post-bake Vt window is close to 8V. There is still a 2V margin from our design spec which is 6V. Operation disturb life time was extrapolated from an accelerated test. AC life time is greater than 2000 years. For some high security applications we provide a user-verify feature. Based on accelerated testing we have proposed the number of user verifies and predicted the error rate.

User verify and disturb mechanisms in a 65nm flash FPGA

We present a study of the disturb mechanism encountered in a novel user verify technique that can be used to enhance the security of a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. Two disturb mechanisms are studied in detail. The intrinsic disturb mode is related to Fowler-Nordheim (FN) tunneling, whereas an extrinsic disturb mode involves traps which enhance the tunneling probability. The effect of single and multiple positive charges is simulated. It is concluded that multiple charges are involved during disturb to explain the observed extrinsic behavior. Accelerated testing predicts that 10k verify operations can be performed with an error rate less than 1ppm for a five million gate FPGA, equivalent to a FIT rate of approx. 0.001 failures per 109 hours per million gates when applied over a 20 year lifetime. The low verify-induced error rate makes the technique suitable for enhancing security by providing timely detection of malicious tampering attacks.