Kyung-Sub Son

On-chip jitter tolerance measurement technique for CDR circuits

We propose an on-chip circuit technique to characterize jitter tolerance of binary clock and data recovery (CDR) circuit. The proposed jitter modulation scheme incorporates modulating-charge-pump and pulse-generator circuits to apply a periodic triangular voltage directly to the control voltage. The range of the modulated jitter amplitude is 0.05-2 UIpp at 10 MHz, and the frequency range is 100 KHz-20 MHz. The CDR circuit was fabricated in 65 nm CMOS, and the jitter tolerance was successfully measured at 5 Gbps with a 27-1 PRBS pattern, The accuracy is within 23% of the theoretical limit. The whole CDR circuit consumes 29.9mW at a supply voltage of 1.2 V.

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS

This paper presents a low-power half-rate clock-embedded transceiver architecture that employs quarter-rate multiplexing/de-multiplexing circuit technique, low-Vdd current-mode driver topology embedding halfrate clock, and multi-functional injection-locked oscillator (ILRO) for a digital clock and data recovery (CDR) design. The whole transceiver circuit was simulated in 65 nm CMOS process and its feasibility was proved successfully operating at 10Gb/s across a band-limited channel. The achievable power efficiencies of the receiver and transceiver were 0.7mW/Gb/s and 1.1mW/Gb/s respectively.

A 200 Mb/s-3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

This paper presents a 200-Mb/s to 3.2-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180nm CMOS process. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking and reduce the frequency acquisition time. A frequency band selector for wide-range the voltage-control oscillator (VCO) is also presented to select an exact frequency band of the VCO. The simulation shows the CDR achieves 11-ps peak-to-peak jitter at 3Gb/s and the frequency acquisition time of 11.8 μs.

A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector

Thispaper presents a 200-Mb/s to 3-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180nm CMOS process. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking issue and reduce the frequency acquisition time. A frequency band selectorfor wide-range the voltage-control oscillator (VCO) is also presented to select an exact frequency band of the VCO. The simulation shows the CDR achieves 10-ps peak-to-peak jitter at 3Gb/s and the frequency acquisition time of 12.9 μs.

A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's

This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric VCOs. Compared with the conventional structure with a T/2 delay cell based approach, the proposed structure shows the better re timing margin without any delay unit for the timing control. The proposed circuit is designed and simulated in 350nm CMOS process. The simulation of the proposed CDR showed the data recovery at 1.6 Gb/s with 27-l pattern with peak-to-peak jitter of 5.5ps.

A Burst-mode Clock and Data Recovery Circuit with Two Symmetric Quadrature VCO's

This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric quadrature phase VCO’s. The reduced loop locking time of less than 5 bits was achieved without any extra delay circuits which are added in conventional schemes for timing control. The proposed circuit is designed in 350 nm CMOS process and its feasibility has been proved successfully operating at 1.25Gb/s.

Precise time-difference repetition for TDC with delay mismatch cancelling scheme

This paper presents a precise time-difference repetition technique to enhance the timing accuracy in repetition based time-to-digital converters (TDC). In the proposed scheme, any delay mismatches during timing difference repetition process can be removed. The proposed circuit could be used for multi-step TDC, delta-sigma TDC, and SAR-type TDC. The proposed scheme was designed and simulated with a 65-nm CMOS process. The proposed circuit shows a delay variation of about 100 fs in the presence of device mismatches, which is much less than that of conventional approaches. The input time range and the conversion rate is 480 ps and 100Msps if applied to a 2-step TDC, respectively.

A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS

The rapid growth of the data rate in serial links reveals the problem of power consumption, motivating utilization of low power building blocks. This paper presents a low-power clock and data recovery (CDR). By employing dynamic CML latch which draws a current during half of the clock cycle and voltage-to-current(V/I) converter which performs the XOR function itself, power reduction in phase detector(PD) is achieved. The CDR circuit is simulated using 5-Gb/s data with 0.18-μm CMOS technology, and the circuit consumes 8.7mW from a 1.8-V supply.

Auto-delay offset cancellation technique for time difference repeating amplifier

This paper presents an auto-delay offset cancellation technique for time difference repeating amplifier. Pipeline time-to-digital converter (TDC) achieves fine resolution by amplifying the time residue. Therefore the linearity of the time difference amplifier (TA) is important in pipeline TDC. The pulse-train TA, time difference repeating amplifier, was proposed to improve this recently. However, it is hard to get accurate gain in TA because there are many possible mismatch issues. Our work makes the delay offset be cancelled automatically during time difference repetition. The proposed circuit is designed and simulated in 65nm CMOS process. The conversion rate is 100Msps and it has 300ps input time range. The proposed scheme shows the delay offset of about 10fs, which is much less than that of the conventional scheme (~100ps) under the equivalent device mismatch conditions.