Jin-Ku Kang

SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators

This letter describes a spread spectrum clock generator (SSCG) circuit with the Hershey-Kiss modulation profile using two stacked sigma-delta modulators. The proposed Hershey-Kiss profile modulator generates various slopes to achieve non-linear modulation profile. Since the modulators are implemented by digital blocks, it can be modified for other applications. Simulation results show that peak power reduction level of 10.2dBm with 5000ppm down spreading at the 340MHz operation using 0.13m CMOS.

An 8B/10B encoder with a modified coding table

This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using CMOS 0.18 mum process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 mum2 with 189 logic gates. It consumes 2.74 mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%.

A design of DisplayPort link layer

This paper presents an implementation of DisplayPort 1.1 Link Layer. The DisplayPort link layer provides isochronous transport service, link service, and device service. Isochronous transport service in source device maps the video and audio streams into the main link under a set of rules, so that the stream can be properly reconstructed to original format and synchronized by the sink device. The link service is used for discovering, configuring, and maintaining the link by accessing DPCD via AUX CH. The main link transmitter and receiver is implemented with 4,820 ALUTs and 4496 register, 557,110 of block memory bits synthesized using Quartus II at Altera Stratix II GX board and can be operated at 200.32 MHz. Also, the AUX-CH block is implemented with 765 ALUTs and 298 register, respectively.

Low-power non-coherent data and power recovery circuit for implantable biomedical devices

In this paper, we present a low-power non-coherent amplitude shift keying (ASK) and phase shift keying (PSK) demodulators with inductive power self-recovery system, and the data-clock recovery circuit for implantable biomedical devices. Both circuits use different coupling factors k from 0.1 to 0.5 in ASK and 0.5 in PSK for inductive link The recovered power regulator that consists of a beta multiplier reference (BMR) with band-gap uses the bridge rectifier output as an unregulated DC input, and produces from 1.73 to 1.8 V regulated output for the demodulator with 2 MHz carrier. The PSK demodulator uses a new demodulation method that uses signals from two differential comparators with low-pass pre-filtered (LPPF) and high-pass pre-filtered (HPPF) outputs for detecting phase changing edges to recover data and clock signals. The full wave detecting signals are used as differential inputs in LPPF comparator of the ASK demodulator. The results of the demodulators with the self-power supply show up to less than 62 μW and 115 μW power consumption in ASK and PSK at 1 Mbps data transfer rate.

High-speed 8B/10B encoder design using a simplified coding table

This letter presents a high-speed 8B/10B encoder design using a simplified coding table. The proposed encoder also includes a modified disparity control block. Logic simulation and synthesis have been done for the performance verification. After synthesized with a CMOS 0.18µm process, the proposed design shows the operating frequency of 343MHz with no latency. The synthesized chip area is 1886µm2 with 189 logic gates. The proposed 8B/10B encoder shows the overall performance improvement compared to previous approaches.

A clock recovery circuit using half-rate 4/spl times/-oversampling PD

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4/spl times/ oversampling phase detector (PD) structure is described. The PD is designed by the 4/spl times/ oversampling method. The PD finds the data-lead and data-lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. The proposed circuit is designed using the TSMC 0.25 /spl mu/m CMOS technology and operating voltage is 2.5V. The circuit operates between 480 Mbit/s-1.5 Gbit/s.

A CMOS clock and data recovery with two-XOR phase-frequency detector circuit

This paper describes a 1.0 Gbps Clock and Data Recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45/spl deg/. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 /spl mu/m-CMOS HSPICE simulation. The circuit is under fabrication. The measured results are presented.

A low power BPSK demodulator for wireless implantable biomedical devices

This paper describes a low-power non-coherent BPSK demodulator for implantable biomedical devices. The proposed demodulator adopts the dual band filtering technique and a digital deglitching circuit for recovering the timing and data. The circuit has been fabricated with a 0.18μm CMOS technology and power consumption of the proposed demodulator is 82μW with a 2MHz carrier frequency achieving 1Mbps data rate on the 250μA internal load.

An ultra-low power BPSK demodulator with dual band filtering for implantable biomedical devices

In this letter, a low-power non-coherent BPSK demodulator which is applicable to implantable biomedical devices is described. The proposed demodulator adopts the dual band filtering for recovering the timing and data in non-coherent way. The circuit has been fabricated with a 0.18 m CMOS technology and the power consumption of the proposed demodulator is measured at 82 Wwith a 2MHz carrier frequency achieving 1Mbps data rate.

An audio clock regenerator with a wide dividing ratio for HDMI

This paper presents a clock regenerator using two 2nd order Σ-Δ (sigma-delta) modulators for wide range of dividing ratio as HDMI standard. The proposed circuit adopts a fractional-N frequency synthesis architecture for PLL-based clock regeneration. The source device sends N (Dividing ratio of video clock to TMDS clock) and CTS (Cycle Time Stamp) values to the sink device for regenerating the audio clock. By processing the integer and fractional part of the N and CTS values separately at two different Σ-Δ modulators, the proposed circuit covers a very wide range of the dividing ratio as HDMI standard and occupies small chip area. The circuit is fabricated using 0.18um CMOS and shows 13mW power consumption with on-chip loop filter.