Kyungmin Lee

Unilamellar Nanosheet of Layered Manganese Cobalt Nickel Oxide and Its Heterolayered Film with Polycations

The exfoliation of layered Li[Mn(1/3)Co(1/3)Ni(1/3)]O(2) into individual monolayers could be achieved through the intercalation of quaternary tetramethylammonium (TMA(+)) ions into protonated metal oxide. An effective exfoliation occurred when the TMA(+)/H(+) ratio was 0.5-50. Reactions outside this range produced no colloidal suspension, but all the manganese cobalt nickel oxides precipitated. Atomic force microscopy and transmission electron microscopy clearly demonstrated that exfoliated manganese cobalt nickel oxide nanosheets have a nanometer-level thickness, underscoring the formation of unilamellar nanosheets. The maintenance of the hexagonal atomic arrangement of the manganese cobalt nickel oxide layer upon the exfoliation was confirmed by selected area electron diffraction analysis. According to diffuse reflectance ultraviolet--visible spectroscopy, the exfoliated manganese cobalt nickel oxides displayed distinct absorption peaks at approximately 354 and approximately 480 nm corresponding to the d-d transitions of octahedral metal ions, which contrasted with the featureless spectrum of the pristine metal oxide. In the light of zeta potential data showing the negative surface charge of manganese cobalt nickel oxide nanosheets, a heterolayered film of manganese cobalt nickel oxide and conductive polymers could be prepared through the successive coating process with colloidal suspension and polycations. The UV--vis and X-ray diffraction studies verified the layer-by-layer ordered structure of the obtained heterolayered film, respectively.

Synthesis and Electrochemical Characterization of Reduced Graphene Oxide-Manganese Oxide Nanocomposites

【Nanocomposites of reduced graphene oxide and manganese (II,III) oxide can be synthesized by the freeze-drying process of the mixed colloidal suspension of graphene oxide and manganese oxide, and the subsequent heat-treatment. The calcined reduced graphene oxide-manganese (II,III) oxide nanocomposites are X-ray amorphous, suggesting the formation of homogeneous and disordered mixture without any phase separation. The reduction of graphene oxide to reduced graphene oxide upon the heat-treatment is evidenced by Fourier-transformed infrared spectroscopy. Field emission-scanning electronic microscopy and energy dispersive spectrometry clearly demonstrate the formation of porous structure by the house-of-cards type stacking of reduced graphene oxide nanosheets and the homogeneous distribution of manganese ions in the nanocomposites. According to Mn K-edge X-ray absorption spectroscopy, manganese ions in the calcined nanocomposites are stabilized in octahedral symmetry with mixed Mn oxidation state of Mn(II)/Mn(III). The present reduced graphene oxide-manganese oxide nanocomposites show characteristic pseudocapacitance behavior superior to the pristine manganese oxide, suggesting their applicability as electrode material for supercapacitors.】

A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology

A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBΩ transimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.

A Multi-Channel Current-Mode CMOS Optical Receiver Array for Active Optical HDMI Cables

This paper introduces a four-channel optical receiver array implemented in a standard 1P4M 0.18μm CMOS technology for the applications of active optical HDMI cables. Each channel consists of a current-mirror transimpedance amplifier, a five-stage differential limiting amplifier, and an output buffer, demonstrating 81-dBΩ transimpedance gain, 1.8-GHz bandwidth even with 0.5-pF photodiode capacitance, −18.3-dBm optical sensitivity for 10−12 BER & 0.6-A/W responsivity, and 51.7-mW power dissipation from a single 1.8-V supply. The whole chip occupies the area of 1.35 × 2.46mm2 including pads. The measured eye-diagrams of the array confirms wide and clear eye-openings up to 4.0-Gb/s operations.

A 6.6 mW, −94 dBc/Hz, 1.0-to-4.5 GHz phase-lock loop in 65-nm CMOS

This paper presents a phase-lock loop (PLL) realized in a standard 65-nm CMOS technology, which multiplies a 50-MHz reference to generate 1.0~4.5 GHz clock signals. The proposed PLL consists of a PFD, a charge pump, a 3rd-order LPF, a ring VCO, a 2/3 prescaler, and a 6-bit divider, providing low cost, small area, and wide tuning characteristics. Post-layout simulations reveal that the PLL achieves 1.0~4.5 GHz tuning range, -94-dBc/Hz phase noise at 3 GHz with 1-MHz offset, and 6.6-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 99 × 106 p.m2.

A 10-channel 300-Mb/s/ch replica TIA array with equalizer in 0.18-μm CMOS

This paper presents a 10-channel optical receiver array for Near-InfraRed Spectroscopy (NIRS) Systems. Each channel consists of a replica transimpedance amplifier (TIA) followed by an adjustable linear equalizer (EQ). The replica TIA achieves a high transimpedance gain of 94.6 dBΩ and a bandwidth of 85 MHz. To obtain wider bandwidth, a two-stage fully differential equalizer with tunable capacitor banks is exploited. Post-layout simulations reveal the total transimpedance gain of 100 dBΩ, the -3-dB bandwidth of 200 MHz, and the input noise current spectral density of 2 pA/√Hz for the DC current consumption of 9.4 mW per channel with a single 1.8-V supply. The proposed front-end of NIRS preamplifier is implemented using 0.18-μm CMOS technology.