L.B.A. Hommels

Charge collection studies in irradiated HV-CMOS particle detectors

Charge collection properties of particle detectors made in HV-CMOS technology were investigated before and after irradiation with reactor neutrons. Two different sensor types were designed and processed in 180 and 350 nm technology by AMS. Edge-TCT and charge collection measurements with electrons from 90Sr source were employed. Diffusion of generated carriers from undepleted substrate contributes significantly to the charge collection before irradiation, while after irradiation the drift contribution prevails as shown by charge measurements at different shaping times. The depleted region at a given bias voltage was found to grow with irradiation in the fluence range of interest for strip detectors at the HL-LHC. This leads to large gains in the measured charge with respect to the one before irradiation. The increase of the depleted region was attributed to removal of effective acceptors. The evolution of depleted region with fluence was investigated and modeled. Initial studies show a small effect of short term annealing on charge collection.

A double-sided, shield-less stave prototype for the ATLAS Upgrade strip tracker for the High Luminosity LHC

A detailed description of the integration structures for the barrel region of the silicon strips tracker of the ATLAS Phase-II upgrade for the upgrade of the Large Hadron Collider, the so-called High Luminosity LHC (HL-LHC), is presented. This paper focuses on one of the latest demonstrator prototypes recently assembled, with numerous unique features. It consists of a shortened, shield-less, and double sided stave, with two candidate power distributions implemented. Thermal and electrical performances of the prototype are presented, as well as a description of the assembly procedures and tools.

HVMUX, the High Voltage Multiplexing for the ATLAS Tracker Upgrade

The increased luminosity of the HL-LHC will require more channels in the upgraded ATLAS Tracker, as a result of the finer detector segmentation. Thus, an upgraded and more efficient HV biasing of the sensors will also be needed and is among the many technological challenges facing the ATLAS Tracker Upgrade. A number of approaches, including the sharing of the same HV line among several sensors and suitable HV switches, along with their control circuitry are currently being investigated for this purpose. The proposed solutions along with latest test results and measurements will be described.

Radiation hardness of two CMOS prototypes for the ATLAS HL-LHC upgrade project

The LHC luminosity upgrade, known as the High Luminosity LHC (HL-LHC), will require the replacement of the existing silicon strip tracker and the transistion radiation tracker. Although a baseline design for this tracker exists the ATLAS collaboration and other non-ATLAS groups are exploring the feasibility of using CMOS Monolithic Active Pixel Sensors (MAPS) which would be arranged in a strip-like fashion and would take advantage of the service and support structure already being developed for the upgrade. Two test devices made with the AMS H35 process (a High voltage or HV CMOS process) have been subjected to various radiation environments and have performed well. The results of these tests are presented in this paper.

A double-sided silicon micro-strip Super-Module for the ATLAS Inner Detector upgrade in the High-Luminosity LHC

The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail.

High voltage multiplexing for the ATLAS Tracker Upgrade

The increased luminosity of the HL-LHC will require more channels in the upgraded ATLAS Tracker, as a result of the finer detector segmentation, stemming from the otherwise too high occupancy. Among the many technological challenges facing the ATLAS Tracker Upgrade there is more an efficient power distribution and HV biasing of the sensors. The solution adopted in the current ATLAS detector uses one HV conductor for each sensor, which makes it easy to disable malfunctioning sensors without affecting the others, but space constraints and material budget considerations renders this approach impractical for the Upgraded detector. A number of approaches, including the use of the same HV line to bias several sensors and suitable HV switches, along with their control circuitry, are currently being investigated for this purpose. The proposed solutions along with latest test results and measurements will be described.

The CHESS-2 prototype in AMS 0.35 μm process: A high voltage CMOS monolithic sensor for ATLAS upgrade

CHESS-2 (CMOS HV Evaluation for Strip Sensors) is a novel ASIC strip architecture designed to investigate the feasibility of using HV-CMOS MAPS (Monolithic Active Pixel Sensors) as alternative sensors for the ATLAS Phase-II Strip Tracker Upgrade. The ASIC is optimized for signal processing, hit pixel position encoding and readout. CHESS-2 includes three independent groups of 128 strips composed of 32 pixels each. The pixel includes a charge sensitive amplifier and the first stage of a comparator inside the collecting well. The second stage, the configuration, the encoding and the readout sections are placed at the periphery of the strips. A novel “fast skip” hit encoding logic identifies the first 8 hit pixel positions with a single-bunch time resolution (25 ns) and sends the data to a fast readout circuitry for serialization and transmission on 14 LVDS channels at 320 MHz. Several substrate resistivity variants have been fabricated for a full characterization of the performance aspects.