L. Bacciarelli

Wafer-level vacuum packaged resonant micro-scanning mirrors for compact laser projection displays

Scanning laser projection using resonant actuated MEMS scanning mirrors is expected to overcome the current limitation of small display size of mobile devices like cell phones, digital cameras and PDAs. Recent progress in the development of compact modulated RGB laser sources enables to set up very small laser projection systems that become attractive not only for consumer products but also for automotive applications like head-up and dash-board displays. Within the last years continuous progress was made in increasing MEMS scanner performance. However, only little is reported on how mass-produceability of these devices and stable functionality even under harsh environmental conditions can be guaranteed. Automotive application requires stable MEMS scanner operation over a wide temperature range from -40° to +85°Celsius. Therefore, hermetic packaging of electrostatically actuated MEMS scanning mirrors becomes essential to protect the sensitive device against particle contamination and condensing moisture. This paper reports on design, fabrication and test of a resonant actuated two-dimensional micro scanning mirror that is hermetically sealed on wafer level. With resonant frequencies of 30kHz and 1kHz, an achievable Theta-D-product of 13mm.deg and low dynamic deformation <20nm RMS it targets Lissajous projection with SVGA-resolution. Inevitable reflexes at the vacuum package surface can be seperated from the projection field by permanent inclination of the micromirror.

Design, testing and prototyping of a software programmable I2C/SPI IP on AMBA bus

While power consumption and area occupation are always critical constrains in system-on-chip design, at the same time high communication flexibility is required, due to proliferation of communication protocols. In this work an architecture for an I2C/SPI interface for APB AMBA bus is presented, showing how it is possible to merge flexibility and reduced area occupation. Large part of this work is centered on the testing and FPGA prototyping of this IP. CMOS synthesis results on 0.18 mum standard cell library are also presented

SYSTEM STUDY FOR A HEAD-UP DISPLAY BASED ON A FLEXIBLE SENSOR INTERFACE

This work presents the system study for an innovative and miniaturized head–up display based on a flexible sensor interface for automotive applications. After a brief introduction, in the second section the basic structure of a head–up display is described. Finally, in the third section our specific design is presented.

Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication

Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design problem due to the limited number of available pins (in not Ball Grid Array package) and to the common need of a frequency reduction, especially into systems that require an external System on Programmable Chip (SoPC). In this paper, an ASIC solution based on bi-synchronous FIFO structures for frequency conversion is presented. The proposed bridge involves a custom protocol for the conversion of the transmitted data in low frequency and low width bus. Moreover, it allows managing data transmission with two different priority levels. The module is AHB lite compliant with a number of pins equal to the width of the FIFOs (configurable during implementation phase) and two handshaking signals. Output clock frequency and internal FIFOs dimension are user-defined too.

A programmable and low-EMI integrated half-bridge driver in BCD technology

This paper presents the design and the laboratory results of an integrated half-bridge driver for power electronic systems in a 0.35 mum bipolar CMOS DMOS (BCD) technology. The proposed solution is designed for frequency applications up to several hundred of KHz and it has a driving current capability up to 50 mA. This work features a design configuration and a digital control to reduce electromagnetic interference (EMI). Moreover it includes short circuit protection, programmability of voltage references and a digital control circuitry implementing mechanism to prevent dangerous failures of the driver. After a deep description of the circuit we show the laboratory results of the half-bridge driver used to drive a 20 KHz antenna.

FPGA-based Advanced Digital Signal Inspector for internal signals of pin-limited systems-on-package

The paper presents an Advanced Digital Signal Inspector (ADSI) used for acquisition and analysis of the internal digital of a System on Package (SoP) with a limited number of pins. The system is made of a commercial FPGA-board, connected to the module for data sampling and controlled by PC via USB; a suited graphical interface allows for configuration, multi trace real time data display and post processing. The proposed platform can be used to extract and monitor simultaneously up to 4 digital signals, and an ADC is used to monitor one additional analog signal. The ADSI has been successfully applied for the characterization of an automotive SoP based on a MEM gyro sensor interfaced to an ASIC for proper signal conditioning. The ADC was connected to an external accelerometer to evaluate the module behaviour when applying mechanical shocks.

A Dynamic Clock Switch for Automotive System on Chip

One of the key-points in system on chip (SoC) design is to have the proper clock oscillator. Currently the most used are RC and quartz oscillators. They feature different characteristics in terms of performance, power consumption and cost, both oscillators have their own advantages and drawbacks. Sometimes SoC design would benefit to have both solutions in order to best cope with all requirements. This calls for an integrated architecture to dynamically switch between the two clock signals. In this paper we present a new parametric architecture able to handle a generic number of clock signals allowing the dynamic switch from one clock to the other. The detailed structure is here shown and an accurate timing analysis is also presented to prove its robustness and the absence of glitch on output clock signal. FPGA and 0.35 mum CMOS implementations are presented for an automotive SoC design.

Efficient acquisition and analysis of digital signals in pin-limited system-on-package.

The paper presents an advanced digital signal inspector (ADSI) used for acquisition and analysis of the internal digital of a System on Package (SoP) with a limited number of pins. The system is made of a commercial FPGA- board, connected to the module for data sampling and controlled by PC via USB; a suited graphical interface allows for configuration, multi trace real time data display and post processing. The proposed platform can be used to extract and monitor simultaneously up to 4 digital signals, and an ADC is used to monitor one further analog signal. The ADSI has been successfully applied for the characterization of an automotive SoP based on a MEM gyro sensor interfaced to an ASIC for proper signal conditioning. The ADC was connected to an external accelerometer to evaluate the SoP behaviour when applying mechanical shocks.