Lorenzo Bertini

Hot wire anemometric MEMS sensor for water flow monitoring

This paper presents an application based on a hot wire anemometric sensor in MEMS technology in the field of water flow monitoring. New generations of MEMS sensors feature remarkable savings in area, costs and power respect to conventional discrete devices, but as drawback, they require complex electronic interfaces for signal conditioning to achieve high performances and a high reliability. This anemometric sensor implementation has been developed with ISIF, a platform SoC, aiming to fast prototype a wide range of sensors thanks to its high configurable resources. The presented system achieves good performances with respect to commercial devices, featuring resolution of plusmn0.35% up to plusmn1.76% with repeatability roughly plusmn1% respect to the full scale (0-250 cm/s). Furthermore the proposed system, thanks to the compact size of the sensor, its robustness and its low costs can represent a solution for diffusive monitoring in water distribution networks.

High-throughput, low complexity, parametrizable VLSI architecture for full search block matching algorithm for advanced multimedia applications

In this paper a new VLSI architecture, called ALPHA-B, for the motion estimation full-search algorithm is proposed. It features high throughput/area efficiency and high block size flexibility for a small hardware complexity. This circuit concurrently processes different block sizes, N/2/spl times/N/2 and N/spl times/N, permitting for the Advanced Prediction (AP) option of the H.263/MPEG-4 standards. It is fully parametrizable in terms of block (N) and search area (p) sizes thus allowing for QCIF/CIF/4CIF image format processing. This architecture was implemented on a 0.25 /spl mu/m CMOS technology in order to realize two IP macro-cells to be integrated in single-chip H.263/MPEG coders. The cases of 30 frames/s CIF and 4CIF formats with a search area of -16/+15 were considered. The resulting CIF-format ASIC features a core area of 1.5 mm/sup 2/ for a clock frequency of 72 MHz while the 4CIF-format ASIC is characterized by a core area of 3.84 mm/sup 2/ for a clock frequency of 105 MHz.

Programmable and low power VLSI architectures for full search motion estimation in multimedia communications

In this paper a new VLSI architecture for the implementation of an enhanced full-search motion estimator for multimedia terminals is proposed: beyond the usual algorithm, advanced prediction and static priority options are supported to improve the SNR/bit-rate efficiency. The architecture is parametrizable in terms of block size (N) and maximum search area size (p/sub max/) (the latter being also programmable in the range [1, p/sub max/]) thus permitting the implementation of a family of ICs suitable for QCIF, CIF, 4CIF image format processing. Two ASICs were realized on a 0.25 /spl mu/m, 2.5 V, CMOS technology able to process 30 frames/s QCIF, CIF, 4CIF formats with a search area of -16/+15. The resulting CIF and 4CIF ASICs feature a high throughput vs. area efficiency for a small hardware complexity and power consumption. The former, characterized by a core area of 1.6 mm/sup 2/, is able to process either QCIF and CIF with a clock frequency of 18 and 72 MHz, respectively, and with an estimated power consumption of about 42 and 170 mW. By exploiting the p programmability, it also processes the QCIF with a clock frequency of about 6 MHz and a power consumption of 15 mW resulting of a great interest for wireless multimedia applications. The 4CIF-ASIC is characterized by a core area of 3.9 mm/sup 2/ with a clock frequency of 105 MHz.

A Dynamic Clock Switch for Automotive System on Chip

One of the key-points in system on chip (SoC) design is to have the proper clock oscillator. Currently the most used are RC and quartz oscillators. They feature different characteristics in terms of performance, power consumption and cost, both oscillators have their own advantages and drawbacks. Sometimes SoC design would benefit to have both solutions in order to best cope with all requirements. This calls for an integrated architecture to dynamically switch between the two clock signals. In this paper we present a new parametric architecture able to handle a generic number of clock signals allowing the dynamic switch from one clock to the other. The detailed structure is here shown and an accurate timing analysis is also presented to prove its robustness and the absence of glitch on output clock signal. FPGA and 0.35 mum CMOS implementations are presented for an automotive SoC design.