L. Colalongo

Numerical analysis of poly-TFTs under off conditions

Abstract Polycrystalline silicon thin-film transistors (poly-TFTs) are getting increasingly important for applications in active-matrix flat-panel displays (AMFPDs) and, more generally, for large-area electronics. As the leakage current requirements of poly-TFTs for large area applications become more stringent, it is important to improve our understanding of the physical effects which originate it. The purpose of this work is that of investigating the anomalous behaviour of leakage-currents in poly-TFTs by numerical simulation, taking into account the effect of energy-distributed traps and field-enhanced generation mechanisms. In what follows, we show that the off current is due to the concomitant effects of Poole-Frenkel, trap-assisted and band-to-band tunneling generation mechanisms, and that each of them may be important at different temperature and bias conditions.

Analysis of conductivity degradation in gold/platinum-doped silicon

A general model is presented, describing the effects of gold/platinum doping in silicon. The steady-state case is then analyzed with reference to the conductivity degradation due to deep impurities in realistic cases of n- and p-type materials. In particular, the different influence of gold with respect to platinum in n-type material, due to the localization in energy of the two acceptor levels, is quantitatively explained and reproduced.

Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors

Polysilicon thin-film transistors are of great interest for their application in large area microelectronics and especially for their circuit applications. A successful circuit design requires a proper understanding of the electrical characteristics and in the present work some specific aspects related to the hot-carrier induced electrical instabilities are presented. In particular, generation of interface states near the drain junction occurs when the devices are operated for a prolonged time in the so-called kink regime. In the present work we show both experimentally and by numerical simulations how the presence of such interface states affects the electrical characteristics. Furthermore, a novel simple method is proposed to extract, from the analysis of the sheet conductances, the interface state density. The hot-carrier induced interface state density relative to the present devices shows a featureless continuous distribution. Reduction of the generated interface states is observed if trapped holes a...

Analysis of electrical characteristics of polycrystalline silicon thin-film transistors under static and dynamic conditions

Abstract Polycrystalline silicon TFT technology is rapidly emerging for large-area electronic applications, because of the relatively large mobility values of charge carriers with respect to the corresponding values in amorphous silicon. In contrast, because of the complex energy distribution of localized states within the energy gap, and the resulting space-charge effects, the TFT electrical characteristics are difficult to model, and a numerical approach is needed in order to better understand the physical effects which influence the device performances. In this article we perform numerical simulations of TFTs at different temperatures under static and dynamic conditions and, by fitting experimental data, extract the energy distribution and the capture cross-section of the grain-boundary traps and the parameters of the impact-ionization model. As opposed to single-crystal silicon SOI devices, we find that the TFT current and transconductance increase as temperature increases.

Dynamic modeling of amorphous- and polycrystalline-silicon devices

The materials of which thin-film transistors (TFTs) are fabricated are characterized by a large amount of defects, giving rise to localized states with a complex energy distribution within the gap. As a consequence, the electrical characteristics of TFTs are difficult to model analytically, and a numerical approach may be preferred to predict their performance. A new efficient method is presented to solve the time-dependent semiconductor equations accounting for energy-distributed gap states. Applications are provided to the analysis of realistic devices and inverters.

Numerical analysis of ISFET and LAPS devices

Abstract In this paper, a numerical simulation technique suitable for device-level analysis of ion-sensitive devices (ion-sensitive field-effect-transistor (ISFET) and light-addressable potentiometric sensor (LAPS)) is presented. Models of the charge layers which develop at the electrolyte–insulator interface of an electrolyte insulator-semiconductor (EIS) system are incorporated into the device equations, thus providing a self-consistent picture of charge and field distribution within the semiconductor domain. To accomplish the simulation of LAPS devices, an AC-modulated optical generation rate has been introduced as well. A TCAD tool, based on the proposed approach, has been developed, which allows for the electrical characterization and for the extraction of circuit-simulation parameters of ion-sensitive devices. Validation of the device-analysis technique comes from the comparison between predicted electrical responses and actual device measurements.

Surface mobility in silicon at large operating temperature

An experimental investigation on high-temperature carrier mobility in silicon inversion layers is carried out with the aim of improving our understanding of carrier transport at the onset of second breakdown. Special MOSFET structures suitable for Hall measurements were designed and manufactured using the BCD-3 technology available at ST-Microelectronics. Hall measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology allowing for the determination of the Hall factor and the carrier mobility against impurity concentration and lattice temperature was devised. Finally, a compact mobility model suitable for implementation in device simulators has been worked out, implemented in the DESSIS/sup /spl copy// code and validated within an industrial environment.

AC analysis of amorphous silicon devices

The transport model in semiconductors is examined in the case where the effect of distributed gap states is significant like, e.g., in thin-film transistors. A solution scheme is derived for the two additional continuity equations accounting for the trapped charge such that, without loss of generality, the efficiency of the traditional method implemented in the existing device-analysis codes is kept. The dynamic effect of the trapped charge is then examined in the ac operation of a realistic thin-film device, including the analysis of the interelectrode capacitances.

Cross-talk simulation in CMOS micromachined gas-sensors with electrothermal actuation

Abstract This paper reports about a device-level simulation of the capacitive crosstalk between the actuators and the sensing elements of a resonant-cantilever gas-sensor based on CMOS technology. The results are exploited to propose some improvements in the device design.

A physically-based analytical model for a-Si devices including drift and diffusion currents

A new compact model for a-Si TFTs is proposed. The model is physically based as the relation between the surface and the quasi-Fermi potentials is correctly accounted for, and therefore implicitly accounts for both linear and saturation operating conditions. Among other consequences, the explicit definition of the threshold and saturation voltages as input parameters is not needed.