M. Valdinoci

Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving our qualitative and quantitative understanding of carrier transport under ESD events. Circular van der Pauw patterns, suitable for resistivity and Hall measurements, were designed and manufactured using both the n and p layers made available by the BCD-3 smart-power technology. The previous measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology that allows for the determination of the Hall factor and drift mobility against impurity concentration and lattice temperature has been developed. Also, a compact mobility model suitable for implementation in device simulators is worked out and implemented in the DESSIS/spl copy/ code. Comparisons with the mobility models by G. Masetti et al. (1983) and D.B.M. Klaassen (1992) are shown in the temperature range between 25 and 400/spl deg/C.

Numerical analysis of poly-TFTs under off conditions

Abstract Polycrystalline silicon thin-film transistors (poly-TFTs) are getting increasingly important for applications in active-matrix flat-panel displays (AMFPDs) and, more generally, for large-area electronics. As the leakage current requirements of poly-TFTs for large area applications become more stringent, it is important to improve our understanding of the physical effects which originate it. The purpose of this work is that of investigating the anomalous behaviour of leakage-currents in poly-TFTs by numerical simulation, taking into account the effect of energy-distributed traps and field-enhanced generation mechanisms. In what follows, we show that the off current is due to the concomitant effects of Poole-Frenkel, trap-assisted and band-to-band tunneling generation mechanisms, and that each of them may be important at different temperature and bias conditions.

Analysis of conductivity degradation in gold/platinum-doped silicon

A general model is presented, describing the effects of gold/platinum doping in silicon. The steady-state case is then analyzed with reference to the conductivity degradation due to deep impurities in realistic cases of n- and p-type materials. In particular, the different influence of gold with respect to platinum in n-type material, due to the localization in energy of the two acceptor levels, is quantitatively explained and reproduced.

Determination of hot-carrier induced interface state density in polycrystalline silicon thin-film transistors

Polysilicon thin-film transistors are of great interest for their application in large area microelectronics and especially for their circuit applications. A successful circuit design requires a proper understanding of the electrical characteristics and in the present work some specific aspects related to the hot-carrier induced electrical instabilities are presented. In particular, generation of interface states near the drain junction occurs when the devices are operated for a prolonged time in the so-called kink regime. In the present work we show both experimentally and by numerical simulations how the presence of such interface states affects the electrical characteristics. Furthermore, a novel simple method is proposed to extract, from the analysis of the sheet conductances, the interface state density. The hot-carrier induced interface state density relative to the present devices shows a featureless continuous distribution. Reduction of the generated interface states is observed if trapped holes a...

Impact-ionization in silicon at large operating temperature

In this work, electron impact-ionization in silicon is investigated both theoretically and experimentally in the temperature range between 25 and 400/spl deg/C. A new compact model for the impact-ionization coefficient is proposed, which nicely fits the theoretical data from the Boltzmann solver HARM and the available experimental data in the above temperature range. The new model has been validated by simulating the reverse characteristics of junction diodes, and turns out to correctly predict the temperature dependence of breakdown voltage.

Analysis of electrical characteristics of polycrystalline silicon thin-film transistors under static and dynamic conditions

Abstract Polycrystalline silicon TFT technology is rapidly emerging for large-area electronic applications, because of the relatively large mobility values of charge carriers with respect to the corresponding values in amorphous silicon. In contrast, because of the complex energy distribution of localized states within the energy gap, and the resulting space-charge effects, the TFT electrical characteristics are difficult to model, and a numerical approach is needed in order to better understand the physical effects which influence the device performances. In this article we perform numerical simulations of TFTs at different temperatures under static and dynamic conditions and, by fitting experimental data, extract the energy distribution and the capture cross-section of the grain-boundary traps and the parameters of the impact-ionization model. As opposed to single-crystal silicon SOI devices, we find that the TFT current and transconductance increase as temperature increases.

An Analytical, Temperature-dependent Model for Majority- and Minority-carrier Mobility in Silicon Devices

A new analytical model for carrier mobility in silicon is presented, which is strongly oriented to CAD and suitable for implementation in device simulators. The effects of the electric field, temperature, and doping concentration are accounted for. In particular, the model unifies the descriptions of majority- and minority-carrier mobility and includes the full temperature dependence. The effects of a high longitudinal field are included in the conventional velocity-saturation form; the doping dependence is also incorporated in the latter. The model has been worked out starting from a preliminary investigation using a Boltzmann solver, and has been validated by a number of comparisons with published experiments on silicon.

Dynamic modeling of amorphous- and polycrystalline-silicon devices

The materials of which thin-film transistors (TFTs) are fabricated are characterized by a large amount of defects, giving rise to localized states with a complex energy distribution within the gap. As a consequence, the electrical characteristics of TFTs are difficult to model analytically, and a numerical approach may be preferred to predict their performance. A new efficient method is presented to solve the time-dependent semiconductor equations accounting for energy-distributed gap states. Applications are provided to the analysis of realistic devices and inverters.

Investigation on anomalous leakage currents in poly-TFTs including dynamic effects

Field-enhanced off-currents are an important limiting factor of polycrystalline-silicon thin-film transistors (TFTs) which still prevents a wider use of such devices in active-matrix liquid crystal displays (AMLCDs) as switching elements within the pixel matrix. The purpose of this work is that of investigating the anomalously-large leakage currents in poly-TFTs by numerical simulation, taking into account for the effects of energy distributed traps and field-enhanced generation mechanisms. The investigation is carried out both in steady-state and in transient conditions in accordance with the typical timing of the driving circuitry, and accounts for the kinetics of trapped carriers. Furthermore, the influence of material quality and device geometry is investigated. This study shows that the electric field increases by 30% during the off-transition with respect to steady-state. However, drain engineering using either LDD or active-gate structures allows for a substantial decrease of the peak electric-field value in dynamic conditions.

Analysis of amorphous-silicon devices

In recent years, Amorphous-Silicon devices have found interesting applications in large-area devices, such as the driving circuitry for flat-panel displays, scanner and print arrays, or chemical sensors. For this reason, many investigations have been carried out for the purpose of improving their performance, especially as far as stability and speed are concerned. To describe their electrical characteristics, analytical models or ad hoc numerical analyses have been proposed elsewhere. In this paper, the implementation of the model for amorphous silicon within the general-purpose simulator HFIELDS is shown, along with an application to a realistic case.<<ETX>>