L. Forbes

Bonded silicon‐on‐sapphire wafers and devices

Silicon‐on‐sapphire (SOS) has been prepared by direct wafer bonding. The silicon layer was thinned to about 10 μm by mechanical grinding and chemical etching. P‐N junction diodes were fabricated in the bonded SOS and compared with epitaxially grown SOS. The reverse bias leakage current was almost 15× less in the bonded SOS. A generation lifetime of 10 μs can be estimated from the junction leakage. The effects of processing temperatures on the bonded SOS were also studied.

A self-backgating GaAs MESFET model for low-frequency anomalies

A self-backgating GaAs MESFET model which can simulate low-frequency anomalies has been developed by including deep-level trap effects. These cause transconductance reduction due to electron emission from EL2 in the depletion width change at the edge of the Schottky gate junction and the output conductance to increase due to the time-dependent net negative charge concentration in the semi-insulating substrate as a result of self-backgating with the applied signal frequency. This model has been incorporated in PSPICE and includes a time-dependent I-V curve model, a capacitance model, an RC network describing the effective substrate-induced capacitance and resistance, and a switching resistance providing device symmetry. An analytical capacitance model describes the dependence of capacitance on V/sub gs/ and V/sub ds/ and includes the channel-substrate junction modulation by the self-backgating effect. A transit-time delay is also included in the transconductances, g/sub m/ and g/sub mbs/, for model accuracy and to describe the phase shift of S-parameters. Measured data correspond to simulations by this model of the low-frequency anomalous characteristics, voltage-dependent capacitances, and S-parameters of conventional GaAs MESFETs for linear and microwave circuit design. >

Tunneling and thermal emission of electrons from a distribution of deep traps in SiO/sub 2/ (nMOSFET)

Both field-induced, or tunneling, and thermal emission of electrons from deep traps in the gate oxides on n-channel LDD CMOS devices have been observed and characterized. Experimental results show that the deep trapping effects at room temperature are similar to the shallow-level trapping effects observed by others below room temperature. In this case, however, the time constants involved are very long. This model and physical mechanisms can explain the apparent saturation observed under AC stress conditions, and also the differences observed between AC use conditions and DC stress. >

Physical model of drain conductance, g/sub d/, degradation of NMOSFET's due to interface state generation by hot carrier injection

Degradation of analog device parameters such as drain conductance, g/sub d/, due to hot carrier injection has been modeled for NMOSFETs. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g/sub d/ degradation can be calculated from linear region transconductance, g/sub m/, degradation which is usually monitored for hot carrier degradation of MOSFETs. The values of g/sub d/ degradation calculated from g/sub m/ degradation fit well to the measured values of g/sub d/ degradation The dependence of the g/sub d/ degradation lifetime on L/sub eff/ has been also studied, this model also provides an explanation of the dependence on L/sub eff/. The model is then useful for lifetime predictions of analog circuits in which g/sub d/ degradation is usually more important than g/sub m/ degradation. >

Hot-carrier induced series resistance enhancement model (HISREM) of nMOSFET's for circuit simulations and reliability projections

Abstract This paper proposes a physically realizable reliability model of nMOSFETs that is applicable for reliability projections in IC design. We have devised a hot-carrier induced series (drain) resistance enhancement model (HISREM) which is based on the increase of the interface trapped charge (ΔNit) near the drain region and is physically realizable in circuit simulations of the hot-carrier induced degradation under operating conditions. The proposed HISREM requires only one parameter (ΔNit) for reliability projections in IC design without extraction of a set of stressed parameter files. The proposed HISREM s shows a good agreement between the simulation results from SPICE and experiment data of the hot-carrier induced degradation of device characteristics. The HISREM has been demonstrated by employing a NMOS inverter and a conventional CMOS operational amplifier. The HISREM is shown to be much simpler and more efficient for reliability projections in both digital and analog IC design rather than the commercial reliability simulator with parameter degradation models which require extraction of a set of stressed parameter files (i.e., Vto, γ, μo, θ, Vmax, K ).

Annealing effects of carbon in n-channel LDD MOSFETs

The degradation pattern of lightly doped drain (LDD) structure MOSFETs with carbon doping under various steps has been studied. For a carbon-doped LDD device with first- and second-level metal and passivation layer but without any final anneal, the results show that a significant reduction in the shifts of the threshold voltage of MOSFETs with time can be achieved. The authors demonstrate that threshold voltage degradation has been reduced for carbon-doped devices and that a final anneal does not improve the hot-electron degradation of these devices. These results imply the existence of neutral electron traps in the gate oxides of MOSFETs.<<ETX>>

Simulation and analysis of noise in switched capacitor amplifier circuits

Noise is an important factor in switched capacitor amplifiers. There is not a good understanding of device noise in switched capacitor circuits, the basic technique is to use large transistors and capacitance values such that kT/C noise dominates. Besides kT/C noise, however, both device or transistor thermal noise and 1/f noise are contributing factors. Techniques to simulate noise in switched capacitor circuits have only recently become available. These techniques have been applied here to a switched capacitor amplifier as is commonly employed in many analog CMOS circuits. A good comparison is obtained between simulations and analytical techniques. It is apparent that device thermal and l/f noise is an important consideration in switched capacitor circuits

On the theory of 1/f noise of semi-insulating materials

The 1/f noise phenomena associated with devices involving semi-insulating materials, for instance GaAs MESFETs on semi-insulating GaAs, has long been a perplexing problem. In this particular case the 1/f noise corner frequency can be up to 100 MHz before the mean square noise current at the drain is dominated by the Nyquist noise associated with the channel conductance. No reasonable explanation has ever been given, although there are many different theories. 1/f noise is a common phenomena in nature and other devices involving semi-insulating materials. We propose here that this 1/f noise is a bulk phenomena associated with localized high frequency variations and long range low frequency fluctuations, the lowest frequency being limited only by the volume of the material. Specifically the proposal here is that injection of a current I into a semi-insulating material will result in a mean square noise voltage at the point of injection given by v/sub n//sup 2/~=2(kT/q)q/spl Delta/fR(/spl omega//sub c///spl omega/) Volts/sup 2/ where /spl omega//sub c/=1/t/sub t/, for the radian frequencies, /spl omega/, larger than /spl omega//sub c/ which is the reciprocal of the transit time of the carriers. For a long sample and long transit times then this 1/f noise voltage due to current injection will be larger than the Nyquist mean square noise of the sample alone as long as the DC voltage developed across the semi-insulating sample exceeds ((2kT/q)l/sup 2/(/spl omega///spl mu/))/sup 1/2/. This theory then gives the 1/f or 1//spl omega/ frequency dependence. The dc current I might be injected for instance by the substrate current in a GaAs MESFET being injected into the semi-insulating substrate, or gate current in an IGET being injected into the gate insulator. >

Analysis of jitter in clock distribution networks

A technique for the simulation of jitter in clock distribution networks will be demonstrated. Noise is injected as a time domain signal into each driver stage in the clock distribution network and large signal non-linear transient simulations are performed to obtain the distribution of clock periods and the subsequent jitter in the clock signal. In the simplest case the noise is the thermal channel noise of the CMOS driver transistors, and the results can be compared to the simple analytical estimate given by Gray et al.[1994]. It will be shown that there is a good agreement between the simulation results and analytical estimates if a modified analytical formula is used where the simple estimate for delay by Gray et al. is replaced by the observed delay from simulations. The technique can be extended and is directly applicable to other types of noise such as power supply noise.

1/f noise due to temperature fluctuations in heat conduction in bipolar transistors

Abstract Noise is an important consideration in the reliability of microelectronic circuits and often sets a lower bound on their sensitivity and limits operation. High device temperature which result from high power operation is shown to result in an additional noise source or mechanism which can become important, become a limiting factor on circuit operation, and limit reliability. Power dissipation at high currents and voltages in bipolar transistors results in significant heat generation and heat conduction towards the heat sink. As might be expected the device temperature is only an average value and there are, as a consequence of the diffusion equation for heat flow itself, temperature fluctuations about this average value. It will be shown that these temperature fluctuations can result in 1/ f noise at moderately low frequencies where these frequencies are determined by the physical dimensions over which the heat flows and the diffusion transit time. This physical phenomena is another mechanism which can be explained by the equivalent circuit representations to obtain frequency dependent solutions to the diffusion equation. The results presented here are then related to the shot noise or white noise due to the collector current allowing a determination of the l/ f noise corner frequency.