Labonnah F. Rahman

Design of an EEPROM in RFID tag: Employing mapped EPC and IPv6 address

In this paper, an approach of RFID tag EEPROM circuit design is presented. The method of designing such tag EEPROM circuit with other tag modules is discussed. The main purpose of this paper is to discuss RFID tag EEPROM circuit modules based on the mapped EPC-IPv6 address format. Also, direct mapping procedure of EPC 64 bit with IPv6 address structure is presented, which will provide a universal identification number to the objects, physical location identification with seamless global mobility. The proposed methodology focused on the process of future EEPROM chip circuit to fabricate without impacting cost and/or data rates.

Designing a ring-VCO for RFID transponders in 0.18 μm CMOS process.

In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

High-Speed Current dq PI Controller for Vector Controlled PMSM Drive

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era.

Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.

A High-Speed and Low-Offset Dynamic Latch Comparator

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm × 59.70 μm.

A Time Series Based Sequence Prediction Algorithm to Detect Activities of Daily Living in Smart Home

OBJECTIVES The goal of smart homes is to create an intelligent environment adapting the inhabitants need and assisting the person who needs special care and safety in their daily life. This can be reached by collecting the ADL (activities of daily living) data and further analysis within existing computing elements. In this research, a very recent algorithm named sequence prediction via enhanced episode discovery (SPEED) is modified and in order to improve accuracy time component is included. METHODS The modified SPEED or M-SPEED is a sequence prediction algorithm, which modified the previous SPEED algorithm by using time duration of appliances ON-OFF states to decide the next state. M-SPEED discovered periodic episodes of inhabitant behavior, trained it with learned episodes, and made decisions based on the obtained knowledge. RESULTS The results showed that M-SPEED achieves 96.8% prediction accuracy, which is better than other time prediction algorithms like PUBS, ALZ with temporal rules and the previous SPEED. CONCLUSIONS Since human behavior shows natural temporal patterns, duration times can be used to predict future events more accurately. This inhabitant activity prediction system will certainly improve the smart homes by ensuring safety and better care for elderly and handicapped people.

Low power D flip-flop serial in/parallel out based shift register

The paper demonstrates the circuit of a low power D flip-flop serial in/parallel out (DFF SIPO) based shift register design. The flip-flops (FFs) consumption of casual logic power in a SoC chip (system on chip) commonly overpasses 50% as long the input and the output are in the same state thanks to the redundancy transition of interior loops. Conventional implementation of shift register systems such as linear feedback shift registers (LFSR) have two main drawbacks namely that elements into structure have been clocked during every clock cycle, and throughput is confined to just one (1) bit per clock cycle. Large scale integrated systems have much higher power consumption when tested due to the increased level of circuit activity. The higher rate of circuit activity can help reduce transition times that are from the input to the output phases. Flip-flops have been performed in 0.18μm CMOS technology. Circuit simulations with displays showing appropriate power dissipations have been reduced are possible where input signals decrease switching activities. A 16-Bit shift register is shown as an easy low power usage.

A Low Voltage Charge Pump Circuit for RFID Tag EEPROM

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in low-voltage applications like RFID tag EEPROM. The improved charge pump circuit has been used as a part of the power supply section of fully integrated radio frequency identification(RFID) transponder IC, which has been implemented in a 0.18-um CMOS process. The modified charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The measured output voltage of the enhanced four-stage charge pump circuit with each pumping capacitor of 1pF to drive the capacitive output load is around 5.62V power supply (VDD) voltage.

Circuit of an EEPROM sense amplifier in 0.18 µm CMOS technology

A sense amplifier for EEPROM memory competent of functioning under a very low-voltage power supply is presented. The sense amplifier was designed for an EEPROM realized with a 0.18-µm CMOS technology. Key design techniques of power dissipation optimization for EEPROM memory are described. The topology of the sense amplifier uses a pure voltage-mode comparison allowing power supply at 1 V to be used. Simulation results showed that the circuit is able to work under a low power and also the size of the circuit is reduced due to the 0.18-µm CMOS process.

Design of a Non-Overlapping Clock Generator for RFID Transponder EEPROM

A non-overlapping clock (NOC) generator circuit is designed for the successful operation of high voltage generator (HVG) implementation in low-power applications like radio frequency identification (RFID) tag EEPROM. The NOC generator has been implemented in 0.18 μm CMOS process. The designed NOC can generate two stable anti-phase clock signals as output, which is used in charge pump (CP) circuit with low power dissipation. The NOC generator required lower power dissipation with 359.87 nW under power supply voltage (VDD) 1.8 V. Moreover, this designed NOC generator produced faster clock signals with 0.972 μS as the settling time.