Lai Jinmei

A high-performance reconfigurable 2-D transform architecture for H.264

The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2-D architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 um CMOS technology. The proposed design is more efficient than the existing typical designs. Under a clock frequency of 100 Mhz, the architecture allows the real-time processing of 4096times2048 at 60 fps.

Design and implementation of the configuration circuit for FDP FPGA

This paper presents a configuration circuit used in the FDP (FDP: Fu Dan Programmable device) FPGA chip. This circuit could write configuration data into FDP and read back data from FDP successfully. Comparing with Xilinx Virtex Series FPGA chips, the smallest configuration section of which is one data-frame, the proposed circuit could write each single memory cell in FDP, providing more flexible configuration operations. A standard configuration interface, Serial Peripheral Interface (SPI), is added in this circuit to replace using the expensive Xilinx Platform configuration Flash PROMs. A group of high precise sensitive amplifiers is adopted in this configuration circuit, which are used to magnify the read back data values. Through a novel write/read asynchronous FIFO structure in FDP, which divides the external interface and internal configuration circuit into two clock domains, designers could set the external clock and internal clock separately. Basic functions of the configuration circuit have been correctly verified by Altera DE2 development board platform. The post layout simulation results indicate via this configuration circuit, each data frame in FDP could be written in 4 mus, and could be read back in 5 mus. The total configuration time of FDP chip is about 6.5 ms.

Iterative solution of ODE-PDE-AE systems for RF circuit simulation

We consider the numerical solution of a system of ordinary differential equations, partial differential equations and algebraic equations arising from simulation of radio frequency circuits in which the transistors are described by partial differential equations. An iterative algorithm is presented together with new techniques to find a good initial guess of the solution. The algorithm is applied to the simulation of a voltage-controlled oscillator and the results are compared with those obtained by MEDICI.

Simulation of RF circuits with a PDE model of the MOSFET

We present an iterative algorithm to compute the response of an RF circuit in which the MOSFET is modeled by a system of partial differential-algebraic equations, rather than an equivalent circuit. The problem amounts to the solution of a nonlinear PDE coupled to a linear ODE. We illustrate the algorithm with the simulation of the Colpitts oscillator.

Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism (NMOS-to-PMOS, PMOS-to-NMOS and NMOS-to-NMOS) and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are: (1) with the exception of PMOS-to-PMOS, pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process. (2) Pulse quenching in general correlates weakly with ion LET, but strongly with incident angle and layout style (i.e. spacing between transistors and n-well contact area). (3) Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

Fast configuration architecture of FPGA suitable for bitstream compression

In this paper, fast configuration architecture of FPGA suitable for bitstream compression is proposed and implemented for FDP2009-II-SOPC (FDP2009-II-SOPC: Fudan Programmable device 2009-II-SOPC) FPGA with SMIC 0.13 CMOS process. This circuit features an addressable configuration register and the internal frame decoder that makes a 32-bit memory cell of FPGA addressable. The improved configuration circuit which can configuration every 32bit memory cells could provide faster configuration speed and more flexible partial configuration operations. The die size of FDP2009-II-SOPC is about 6.3mm*4.5mm=28.35mm2 and the area of this configuration circuit is about 1.7mm2. The post layout simulation shows that this fast configuration circuit of FDP2009-II-SOPC FPGA could work correctly and efficiently and the configuration time is less than 53% of that of Xilinx VirtexII series FPGA1.

Circuit design of a novel FPGA chip FDP2008

A novel FPGA chip FDP2008 (Fudan Programmable Logic) has been designed and implemented with the SMIC 0.18 μm CMOS logic 1P6M process. The new design method means that the configurable logic block can be configured as distributed RAM and a shift register. A universal programmable routing circuit is also presented; by adopting offset lines, complementary hanged end-lines and MUX + Buffer routing switches, the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. A standard configuration interface SPI is added in the configuration circuit, and a group of highly sensitive amplifiers is used to magnify the read back data. FDP2008 contains 20 × 30 logic TILEs, 200 programmable IOBs and 10 × 4 kbit dual port block RAMs. The hardware software cooperation test shows that FDP2008 works correctly and efficiently.

A new FPGA with 4/5-input LUT and optimized carry chain

A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources. We also develop a new carry chain structure with an optimized critical path. Finally a newly designed configurable scan-chain is inserted. The circuit is fabricated in 0.13 μm 1P8M 1.2/2.5/3.3 V logic CMOS process. The test results show a correct function of 4/5-input LUT and scan-chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 72.5%. Our results also show that the logic utilization of this work is better than that of a Virtex II/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex II/Virtex 4 FPGA when implemented using only 5-LUT.

A new FPGA architecture suitable for DSP applications

A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

A delay-optimized universal FPGA routing architecture

A universal FPGA routing Architecture is presented, which ensures that every module in the FPGA including CLBs and IOBs have a uniform interconnect architecture, and the load of interconnect lines is equally distributed. So, this architecture is highly repeatable and the signal delay is predictable and regular. Furthermore, the realization of the Programmable Interconnect Point (PIP) and the BUFFER driver is also optimized to benefit the signal delay up to 5%. The test results of the example chip show the reasonableness of these ideas.