Min Hao

A high-performance reconfigurable VLSI architecture for vbsme in H.264

VBSME (variable block size motion estimation) is adopted in the MPEG-4 AVC/H.264 standard. In order to increase the hardware utilization for VBSME with FSBMA (full search block matching algorithm), this paper proposed a new high-performance reconfigurable VLSI architecture to support meander-like scan format for a high data reuse of search area. The architecture can support the three data flows of the scan format through a reconfigurable computing array and a memory of the search area. The computing array can achieve 100% processing element (PE) utilization and can reuse the smaller blocks SADs to calculate 41 motion vectors (MVs) of a 16X16 block in parallel. The design is implemented with TSMC 0.18 mum CMOS technology. Under a clock frequency of 180 MHz, the architecture allows the real-time processing of 1280 x 720 at 45 fps in a search range [-16, +16].

Design of low-power baseband-processor for RFID tag

This paper analyzes the power consumption of an RFID tag and presents a new architecture of a low-power baseband-processor for this special passive tag. The tag consists of a power reception system, an emitter/receiver analog module, an EEPROM and a low-power baseband-processor, compatible with the newest EPCtrade C1G2 UHF RFID protocol. Meanwhile some novel and advanced low-power technologies are adopted for the special low-power baseband-processor, which not only implements the anti-collision schemes and authorization scheme, but also executes read/write operation to EEPROM. The chip was designed and fabricated using 0.35 mum 3 metal layers CMOS technology successfully

High efficient rectifier circuit eliminating threshold voltage drop for RFID transponders

A high efficient rectifier circuit eliminating threshold voltage drop is presented. Based on conventional full wave bridge rectifier circuit, this rectifier circuit uses bootstrapped circuit technique, so it conquers the problem of threshold voltage drop in conventional rectifier circuit. The characteristic of high efficiency and compatibility with standard CMOS process make the rectifier circuit suitable for RFID transponders where high efficient rectifier circuit is much required

A high-performance reconfigurable 2-D transform architecture for H.264

The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A high-performance reconfigurable 2-D architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 um CMOS technology. The proposed design is more efficient than the existing typical designs. Under a clock frequency of 100 Mhz, the architecture allows the real-time processing of 4096times2048 at 60 fps.

A novel baseband-processor for LF RFID tag

A novel baseband-processor for LF RFID tag compatible with ISOl 1784/11785 is presented. An asynchronous method for data demodulation is proposed to solve the clock halting problem during 100% ASK modulation mode and a new command decoder is designed to increase command decoding speed. Other low-power techniques, such as power management, module reuse and architecture optimization are also implemented to enhance tag interference immunity and to reduce chip area as well as power consumption. The processor is verified on Xilinx Virtex-II Pro real-time verification platform and the results prove the completeness of its designed functionality and its low power consumption. The chip is fabricated using a 0.18 mum 2P4M CMOS standard process with the die area of 300 mum times 300 mum.

Design and VLSI implementation of an asynchronous low power microcontroller

A novel VLSI design and implementation of a low power 8-bit microcontroller using asynchronous logic is proposed in this paper. Taking advantage of the low power potential of asynchronous logic, the 2-stage pipelined MCU is carefully designed by chosen proper architecture as well as suitable asynchronous signal protocols which including a combination of a specific Completion Detection Method and matching delay Method. Other low power design techniques such as Gating Clock also applied to the design. Using synchronous design flow and standard-cell library facilitates the VLSI design and circuit implementation. Fabricated in Chartered 0.6 um CMOS technology, this low power asynchronous MCU achieves only 16% power dissipation of the conventional designed PIC16C61, which shares the same instruction set and function as the MCU we designed.

A novel dynamic reconfigurable VLSI architecture for H.264 transforms

The 4times4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4times4 forward and inverse transforms for H.264 are proposed. A new dynamic reconfigurable architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18 mum CMOS technology. Under a clock frequency of 200 Mhz, the architecture allows the real-time processing of 4096times2048 at 30 fps with the area cost of 5140 gates and the power dissipation of 15.64 mW.

A novel offset compensation biquad switched-capacitor filter design

Based on the architecture of traditional biquad switch-capacitor (SC) filter, placing a low-frequency zero in the transfer function of the filter by the method of adding a SC integral in the feedback path of the circuit, we designed a novel biquad SC filter used in the RFID reader. The new architecture can compensate the DC offset comes from the input and the internal offset originated by the mismatch within the differential circuit of the filter. And the output offset of our design is determined by the input offset of the integrator in the feedback path. The result of simulation show the output offset of this new architecture can be controlled within 30 mv if the input offset change from 50 mv to 500 mv.Based on the architecture of traditional biquad switch-capacitor (SC) filter, placing a low-frequency zero in the transfer function of the filter by the method of adding a SC integral in the feedback path of the circuit, we designed a novel biquad SC filter used in the RFID reader. The new architecture can compensate the DC offset comes from the input and the internal offset originated by the mismatch within the differential circuit of the filter. And the output offset of our design is determined by the input offset of the integrator in the feedback path. The result of simulation show the output offset of this new architecture can be controlled within 30 mv if the input offset change from 50 mv to 500 mv.

A 20 Gb/s Limiting Amplifier in 65nm CMOS technology

This paper presents a 20Gb/s Limiting Amplifier (LA) with the active interleaving feedback technique both to broaden the bandwidth and achieve flatness response. The LA includes an input match and DC offset cancellation (DCOC), a four-stage 3rd order amplifier core and an output buffer for test. Simulated in the 65nm CMOS technology, the LA exhibits a voltage gain of 38.5dB, a 3-dB bandwidth of 18GHz and an integrated input noise of 0.56mV with the area of only 0.45 × 0.25 mm2. The chip excluding buffer is supplied by 1.2V VDD and consumes DC power of 61mW.

A Novel reconfigurable VLSI architecture for motion estimation

A new reconfigurable multi-BMA VLSI architecture was proposed to select different levels of trade-off between video quality, computing complexity and power for power aware applications. The architecture can reuse the smaller blocks SADs to calculate 41 motion vectors of a 16times16 block in parallel for H.264s VBSME. TSMC 0.18 um CMOS technology was adopted and the circuits power consumption can be changed between 13.8 and 247 mW with the typical algorithms. Under a clock frequency of 157 Mhz, the architecture allows the real-time processing of VGA at 30 fps with FS in a search range [-16, +15] at the high level.