Larry Clevenger

Silicides and local interconnections for high-performance VLSI applications

As the minimum VLSI feature size continues to scale down to the 0.1–0.2-µm regime, the need for low-resistance local interconnections will become increasingly critical. Although reduction in the MOSFET channel length will remain the dominant factor in achieving higher circuit performance, existing local interconnection materials will impose greater than acceptable performance limitations. We review the state-of-the-art salicide and polycide processes, with emphasis on work at IBM, and discuss the limitations that pertain to future implementations in high-performance VLSI circuit applications. A brief review of various silicide-based and tungsten-based approaches for forming local interconnections is presented, along with a more detailed description of a tungsten-based “damascene” local interconnection approach.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Integrated layout based Monte-Carlo simulation for design arc optimization

Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves design arc, a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

A novel analytical capacitance model for sub-10 nm interconnects

Quick calculation of capacitance without field solver simulations is desirable to evaluate process assumptions and predict interconnect performance with minimal computation time. At sub-10 nm technology nodes complex interconnect stacks and shrinking dimensions preclude the use of empirical formulae. Here, we extend a physically based quick capacitance model to incorporate sub-10-nm technology elements such as damage layers, multilayer dielectric caps and non-rectangular interconnect cross-sections. The computation time of our model, implemented in standard spreadsheet software is negligible and validation with actual 10-nm node interconnect dimensions shows <;1% error to field solver results. Our model also demonstrates good sensitivity to key process parameters. Our results would be useful to enable quick capacitance estimations for technology and process design.

Technology and design architectures and process innovations for 7 and 5nm BEOL interconnects

For a semiconductor technology node, the BEOL definition must support minimal parasitic impact to technology, sufficient reliability, required dimensional scaling from previous nodes for standard cell and custom logic requirements, and high yielding/low cost integration schemes. This talk will discuss the key BEOL elements and innovations in these areas for the 7nm nodes and beyond. The individual elements are often in conflict with each other, but must be considered in unison to determine the overall best definition. For the 7nm node and future nodes, the BEOL resistance and capacitance is a significant portion of the parasitic degradation of overall technology performance. The BEOL resistance does not scale, due to exponential increases in Cu resistivity with technology scaling and Cu diffusion barrier thicknesses which approach their fundamental limits. Challenges for scaling for BEOL capacitance include integration issues which tend to drive the effective dielectric constant higher than the modeled values. BEOL Reliability is challenged by both operation voltage requirements - which are not scaling as fast as pitch scaling - and by non-scaling current requirements which strain electromigration performance. Dimensional scaling historically has been to a certain pitch scale factor from a previous node typically, 0.7 to 0.8. This smaller scaling factor provides a technology density benefit, but causes acute resistance parasitic issues. In addition, scaling to smaller dimensions highlights integration yield/cost issues. In the 7 and 5 nm nodes, the possible patterning approaches are a combination of double or quadruple exposed optical lithography or single or double exposed EUV. Aggressive scaling of pitch pushes patterning further away from known, demonstrated manufacturing solutions and adds risk to overall integration yield and cost targets.

A study of BEOL resistance mismatch in double patterning process

Matched circuit components are widely used in logic circuits including resistors, capacitors and transistors. Any variations in those components could cause mismatch in circuit performance. In advanced technology nodes, double patterning (litho/etch/litho/etch) process has been introduced to pattern BEOL metal and via levels. Two patterning steps (litho/etch/litho/etch) with two sets of masks for litho printing and with two independent etch processes, could result in pattern dimension difference which leads to resistance and capacitance (RC) mismatch. In wire or via heavily dominated logic circuits, this RC mismatch may be sensitive to design-matched circuit components. In this paper, we studied resistance mismatch in 14nm BEOL metal level where the double patterning process is used. The mismatch of metal resistance between two locations with same-mask design and two-mask design are studied. The mismatch systematic mean offset and random variability have been discussed. The methodology of determining whether the mismatch is dominated by systematic mean offset or random variability and how to quantify the mismatch variability has been introduced and discussed in this paper.