Andrew H. Simon

Comparison of Cu electromigration lifetime in Cu interconnects coated with various caps

Electromigration in Cu Damascene lines with bamboo-like grain structures, either capped with Ta/TaN, SiNx, SiCxNyHz layers, or without any cap, was investigated. A thin Ta/TaN cap on top of the Cu line surface significantly improves electromigration lifetime when compared with lines without a cap and with lines capped with SiNx or SiCxNyHz. The activation energy for electromigration increased from 0.87 eV for lines without a cap to 1.0–1.1 eV for samples with SiNx or SiCxNyHz caps and to 1.4 eV for Ta/TaN capped samples.

A high performance liner for copper damascene interconnects

We describe a liner for Cu-Damascene multilevel ULSI interconnects, which satisfies all the important requirements for a high performance and reliable Cu interconnect technology. This liner is implemented in the first manufacturing process to produce and ship CMOS chips with Cu interconnects. The liner is a bilayer from a family of hcp/bcc-TaN followed by bcc-Ta (/spl alpha/-Ta), deposited sequentially in a single PVD chamber from a pure Ta target, using Ar and N/sub 2/ sputtering gases. This bilayer simultaneously maximizes adhesion to the interlevel dielectric and the Cu fill, and has very low in-plane resistivity (/spl sim/30-60 /spl mu//spl Omega/-cm, depending on TaN/Ta thicknesses). These qualities produce high-yield, highly reliable, and electromigration-redundant Cu interconnects.

Effects of overlayers on electromigration reliability improvement for Cu/low K interconnects

Electromigration in Cu Damascene lines capped with either a CoWP, Ta/TaN, SiN/sub x/, or SiC/sub x/N/sub y/H/sub z/ layer was reviewed. A thin CoWP or Ta/TaN cap on top of the Cu line surface significantly reduced interface diffusion and improved the electromigration lifetime when compared with lines capped with SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/. Activation energies for electromigration were found to be 2.0 eV, 1.4 eV, and 0.85-1.1 eV for the Cu lines capped with CoWP, Ta/TaN, and SiN/sub x/ or SiC/sub x/N/sub y/H/sub z/, respectively.

Effect of liner thickness on electromigration lifetime

Electromigration lifetime was measured as a function of liner thickness for Cu/SiO2 interconnect structures. A significant increase in mean lifetime was observed for structures in which the liner thickness at the base of the test via was less than approximately 6 nm, with a current density <5 mA/μm2 in the power line connected to the test via. This is attributed to the continuous flow of Cu across the thin and possibly discontinuous liner at the base of the via. For extremely thin liner coverage, <1.4 nm at the base of the via and 2.5 at the bottom of the test line, the mean lifetime was observed to decrease as a rapid diffusion path was created which partially offset the beneficial effects of continuous flow. Failure distributions appeared to be trimodal and this was confirmed through failure analysis. In the case of thin liner coverage (<6 nm), early fails, which are typically characterized by slitlike voids at the via/line interface, were not observed.

Electromigration in Cu(Al) and Cu(Mn) damascene lines

The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only alloy lines. These results indicated that the existence of bamboo grains in bamboo-polycrystalline lines played a critical role in slowing down the EM-induced void growth rate. The bamboo grains act as Cu diffusion blocking boundaries for grain boundary mass flow, thus generating a mechanical stress-induced back flow counterbalancing the EM force, which is the equality known as the “Blech short length effect.”The effects of impurities, Mn or Al, on interface and grain boundary electromigration (EM) in Cu damascene lines were investigated. The addition of Mn or Al solute caused a reduction in diffusivity at the Cu/dielectric cap interface and the EM activation energies for both Cu-alloys were found to increase by about 0.2 eV as compared to pure Cu. Mn mitigated and Al enhanced Cu grain boundary diffusion; however, no significant mitigation in Cu grain boundary diffusion was observed in low Mn concentration samples. The activation energies for Cu grain boundary diffusion were found to be 0.74 ± 0.05 eV and 0.77 ± 0.05 eV for 1.5 μm wide polycrystalline lines with pure Cu and Cu (0.5 at. % Mn) seeds, respectively. The effective charge number in Cu grain boundaries Z*GB was estimated from drift velocity and was found to be about −0.4. A significant enhancement in EM lifetimes for Cu(Al) or low Mn concentration bamboo-polycrystalline and near-bamboo grain structures was observed but not for polycrystalline-only al...

A high performance 0.13 /spl mu/m copper BEOL technology with low-k dielectric

The integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described. Up to five levels of copper wiring at three different metal pitches is provided in a spin-on organic inter metal dielectric (SiLK/sup TM/ semiconductor dielectric. The Dow Chemical Co.). Additional global wiring levels in fluorosilicate glass (FSG) at two different relaxed metal pitches result in a total of up to eight levels of hierarchical wiring for enhanced BEOL performance. Successful integration was achieved while maintaining reliability standards. Development of new advanced unit processes was required to meet the challenges presented by this work. Patterning and passivation methodologies are discussed. A key feature of the integration scheme and material set reported is the resulting reduction in complexity compared to other proposed low-k integration alternatives for the current generation.

Physical, Electrical, and Reliability Characterization of Ru for Cu Interconnects

Thin film characterization, electrical performance, and preliminary reliability of physical vapor-deposited (PVD) TaN/chemical vapor-deposited (CVD) Ru bilayer were carried out to evaluate its feasibility as a liner layer for back-end of line (BEOL) Cu-low k integration. Adhesion and barrier strength were studied using 4-point bend, X-ray diffraction (XRD), and triangular voltage sweep (TVS) techniques. Electrical yields and line/via resistances were measured at both single and dual damascene levels, with PVD TaN/Ta liner layer as a baseline control. Reliability studies included electromigration (EM) and current-voltage (I-V) breakdown tests

CVD Co and its application to Cu damascene interconnections

Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by AFM) showed correlations with amounts of in-film oxygen/carbon. Cobalt diffused through copper at normal processing temperatures (by SIMS). CVD Co demonstrated diffusion barrier performance to Cu (by Triangular Voltage Sweep, TVS), but not to O2. CVD Co was applied to 32 nm/22 nm damascene Cu interconnect fabrication in a scheme defined by the material studies. Lower post-CMP defect density and longer electromigration lifetimes were obtained.

Electromigration comparison of selective CVD cobalt capping with PVD Ta(N) and CVD cobalt liners on 22nm-groundrule dual-damascene Cu interconnects

Alternate metallization schemes for copper interconnect using selective CVD Co capping at the 22nm technology node are investigated. Control splits fabricated with PVD Ta(N) barrier/liner layers and CuMn alloy seedlayers are compared against interconnects fabricated using a PVD TaN barrier/CVD Co liner scheme with selective CVD Co capping. Secondary ion mass spectroscopy (SIMS) studies of PVD TaN barrier/CVD Co liner structures indicates that top-surface segregation of the Mn-dopant in alloy seedlayers is suppressed in the presence of the CVD Co Liner. Alternate metal capping in the form of selective CVD Co layers is evaluated in combination with CVD Co liners. Good electrical yields are obtained in-line with the Co liner/Co cap scheme. The PVD TaN/Co-Liner/Selective CVD Co cap combination is seen to have greatly enhanced electromigration performance over PVD Ta(N)/PVD CuMn controls, with T50 fail times for the former being ~100x longer than the controls. Kinetics studies of the CVD Co liner/selective Co cap samples show electromigration activation energies of 1.7 eV, a substantial enhancement over the 1.0 eV obtained for the PVD Ta(N)/CuMn controls.

Effects of Contact Area on Mechanical Strength, Electrical Resistance, and Electromigration Reliability of Cu/Low-k Interconnects

The measurement result of mechanical strength from a back end of the line (BEOL) Cu/low-k interconnect is reported and correlates with the electrical resistance and electromigration reliability of the interconnect structure with increased via contact areas. A Cu interconnect structure in ultralarge scale integration circuits forms vias between successive layers by removing material in the top surface of the lower interconnect, extending the via feature down into the lower interconnect and creating cone-shaped apertures. The increased via contact area increases the overall mechanical toughness of the BEOL interconnect, reduces the electrical contact resistance, and enhances the electromigration resistance of the integrated circuit.