Larry G. Jones

CELLERITY: a fully automatic layout synthesis system for standard cell libraries

This paper describes a fully automatic standard-cell layoutsynthesis system, CELLERITY. The system is flexible insupporting a wide variety of process technologies and a range oflibrary template styles. The tool is fully automatic and providesseveral options to the user to customize the layout template. Thetool considers performance and yield and generates dense,design-rule correct layouts. Experimental results indicate that thearea of CELLERITY-generated standard cells is competitive withmanually designed cells in a majority of circuits. In block-leveltests of industrial circuits, standard-cell blocks generated usingCELLERITY cells are about equal to the block area produced byusing a manually-designed library. Recently, an embeddedmicrocontroller in a state-of-the-art sub-micron processtechnology was fabricated using CELLERITY-generated standard cells.

A timing-constrained incremental routing algorithm for symmetrical FPGAs

in this paper we present a timing-constrained routing algorithm for symmetrical FPGAs which embodies a novel incremental routing strategy that combines global and detailed routing, and a routing resource allocation algorithm that takes into account both the characteristics of the routing resources and timing information. Experimental results confirm that the algorithm reduces delay along the longest path in the circuit, uses routing resources efficiently, and requires low CPU time.

A cache-based method for accelerating switch-level simulation

Switch-level simulation has become a common means of validating the behavior of MOS circuits. In this paper, we present a new cache-based simulation method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory, the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables, and significantly reduce the memory requirements. >

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.

Reducing the scheduling cost in event-driven simulation through component clustering

A method to reduce the scheduling overhead is proposed. Circuit elements that are likely to be activated simultaneously are grouped into clusters and are scheduled and evaluated simultaneously. This way, the number of entities involved in the scheduling, and therefore the scheduling overhead, is reduced. Different algorithms for partitioning the circuit into clusters are presented and the relationship between the cluster size and the simulation performance is studied. The algorithms presented were implemented for a switch-level simulator and tested for several large circuit descriptions. It is shown that with a carefully picked cluster size and partitioning algorithm, the scheduling overhead in the simulation can be significantly reduced and the simulation efficiency improved.<<ETX>>