Larry J. Thayer

Scalable graphics enhancements for PA-RISC workstations

The addition of graphics-specific features to the series 700 system architecture has improved graphics performance by 33% to 100% across various graphics workloads relative to the base system architecture. The model 730, which incorporates a 76 SPECmark PA-RISC (reduced instruction set computer) CPU, is capable of rendering over 1,000,000 3D vectors/s and 19400 independently shaded, z-buffered quadrilaterals/s using a simple entry level frame buffer. Further improvements in performance may be obtained by partitioning the graphics pipeline between the CPU and dedicated rasterization and geometry accelerators. Enhancements to the CPU include polygon rasterization with virtual memory z-buffer support, graphics-specific floating-point, and graphics-specific data path features.<<ETX>>

System design for a low cost PA-RISC desktop workstation

A low-cost high-performance desktop workstation is described. A high-performance CMOS processor was developed with the specific goal of moving the PA-RISC architecture into the low-cost workstation market. Not only were each of the system components designed for optimal performance, but they were also designed to support the other system components. The processor added features and instructions to improve graphics performance. The memory system was optimized to minimize the effects of cache misses on the CPU performance and at the same time provide the memory to graphics bandwidth needed to support the most advanced graphics systems. Special hardware was added to the memory controller to allow low-cost 3-D graphics systems to be developed. The I/O system provides the most important industry standard I/O interfaces for low cost and high performance, and also provides an industry standard EISA bus for less common and future I/O needs.<<ETX>>

A guide to engineering workstations: how ICs impact workstations

The process employed by a group of workstation designers in creating a prototype for a high-performance, low-cost workstation is described. The design team moved an existing architecture-the precision-architecture, reduced-instruction-set computer (PA-RISC) design-into the realm of a low-cost desktop computer. The goal was to make a PA-RISC implementation suitable for a high-performance single-user workstation that would provide exceptional application and graphics performance, yet would also provide continuity with existing systems. It is shown how performance goals and design capabilities influenced decisions about what types of ICs should be used.<<ETX>>

System level ASIC design for Hewlett-Packard's low cost PA-RISC workstations

The system architecture of a low cost PA-RISC workstation is described. This architecture is implemented in Hewlett-Packards 9000 series 700 workstations. High performance and low cost are achieved through careful system partitioning and appropriate application of integration. The system design involved the development of four ASICs: a memory I/O system controller, a mixing buffer chip, a DRAM address decoder/buffer chip, and a controller for the built-in I/O functions. The system architecture is optimized to maximize performance for workstation workloads which include an emphasis on raw CPU performance, graphics, and I/O throughput.<<ETX>>