Leith L. Johnson

System design for a low cost PA-RISC desktop workstation

A low-cost high-performance desktop workstation is described. A high-performance CMOS processor was developed with the specific goal of moving the PA-RISC architecture into the low-cost workstation market. Not only were each of the system components designed for optimal performance, but they were also designed to support the other system components. The processor added features and instructions to improve graphics performance. The memory system was optimized to minimize the effects of cache misses on the CPU performance and at the same time provide the memory to graphics bandwidth needed to support the most advanced graphics systems. Special hardware was added to the memory controller to allow low-cost 3-D graphics systems to be developed. The I/O system provides the most important industry standard I/O interfaces for low cost and high performance, and also provides an industry standard EISA bus for less common and future I/O needs.<<ETX>>

PA7300LC integrates cache for cost/performance

HP continues its development of low cost, high performance processors with an evolution of the PA7100LC which includes 128 kB of on-chip primary cache. It implements the full PA-RISC1.1 functionality including the little-endian, uncacheable memory, and multimedia extensions of the PA7100LC. The PA7300LC connects directly to an optional second level cache of 256 kB to 64 MB using plug-in cards. It also adds the ability to accelerate I/O stores to certain memory locations for greatly improved graphics performance. The cache system consists of on-chip, 2-way, separate instruction and data caches of 64 kB total each, plus the off-chip second level cache. Memory consists of 8 MB to 3.75 GB of standard DRAMs or SIMMs connecting directly to the processor chip, using either a 72 bit or 144 bit data path. The chip is fabricated in 0.5 micron, 4-level metal CMOS and is designed to run at frequencies up to 160 MHz. The PA7300LC exceeds performance levels of previous generation high-end workstations while lowering overall system cost and power consumption.

System level ASIC design for Hewlett-Packard's low cost PA-RISC workstations

The system architecture of a low cost PA-RISC workstation is described. This architecture is implemented in Hewlett-Packards 9000 series 700 workstations. High performance and low cost are achieved through careful system partitioning and appropriate application of integration. The system design involved the development of four ASICs: a memory I/O system controller, a mixing buffer chip, a DRAM address decoder/buffer chip, and a controller for the built-in I/O functions. The system architecture is optimized to maximize performance for workstation workloads which include an emphasis on raw CPU performance, graphics, and I/O throughput.<<ETX>>