Lars Braun

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

Dynamic and partial reconfiguration (DPR) is a special feature offered by Xilinx Field Programmable Gate Arrays (FPGAs), giving the designer the ability to reconfigure a certain portion of the FPGA during run-time without influencing the other parts. This feature allows the hardware to be adaptable to any potential situation. For some applications, such as video-based driver assistance, the time needed to exchange a certain portion of the device might be critical. This paper addresses problems, limitations and results of on-chip reconfiguration that enable the user to decide whether DPR is suitable for a certain design prior to its implementation. A method is therefore introduced to calculate the expected reconfiguration throughput and latency. In addition, an IP core is presented that enables fast on-chip DPR close to the maximum achievable speed. Compared to an alternative state-of-the art realization, an increase in speed by a factor of 58 can be obtained.

Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems

Current trends show that in future it will be essential that various kinds of applications are running on one chip. These require an efficient and flexible network on chip which is able to adapt to the demands of supported modules. This makes it necessary to think about what kind of network on chip will meet these requirements. This paper describes an approach for a reconfigurable network on chip which allows adapting the performance and topology at run-time to the demand of the application running on Xilinx FPGA.

Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications

Since the 1990s reusable functional blocks, well known as IP-Cores, have been integrated on one silicon die. These systems-on-chip (SoC) used a bus-based system for intermodule communication. Technology, performance and flexibility issues require the introduction of a novel communication system called network-on-chip (NoC). Around 1999 this method was introduced and since then has been investigated by several research groups with the aim to connect different IP-Cores through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. Since software parts of an electronic system can also be included into reconfigurable hardware by integration of IP-based microcontrollers, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform for HW / SW Co-designs. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for an adaptive circuit switched network-on-chip and the related techniques for adapting the system during run-time to the requirements of the presented image processing application.

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms on-demand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi- and many-core architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switch-based Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many- and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.

Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems

Since the 1990s reusable functional blocks, well known as IP-Cores, were integrated on one silicon die. These systems-on-chip (SoC) used a bus-based system for intermodule communication. Technology and flexibility issues forced to introduce a novel communication system called network-on-chip (NoC). Around 1999 this method was introduced and until then it is investigated by several research groups with the aim to connect different IP-Blocks through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for a multi-layer network-on-chip and the related techniques for adapting the network while run-time to the requirements of an application.

Data path driven waveform-like reconfiguration

The Xilinx Virtex FPGA family provides the capability to perform dynamic partial hardware reconfiguration (DPR). This implies that parts of the system can by dynamically reprogrammed while the rest of the system components continue their execution without being interrupted. Such reconfigurable FPGA systems are becoming more and more common for applications that require a high degree of run-time flexibility. One major research task in this area is to decrease the overhead caused by the reconfiguration duration. This can be done by increasing the reconfiguration rate, which means increasing the system performance when performing the reconfiguration. This paper presents an alternative approach which aims at decreasing the influence of the reconfiguration, by carefully dividing the reconfigurable modules according to the specific data graph and to start processing the data while the following parts of the data graph are still being reconfigured. This prevents data from being stalled and waiting for the reconfiguration to complete. The suggested approach is referred to as waveform-like reconfiguration, since the data processing closely follows the reconfiguration process.

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs

Xilinx Virtex-II / Virtex-II Pro FPGAs provide the possibility of partial and dynamic run-time reconfiguration. This feature can be used in adaptive systems providing the possibility to adapt to application requirements by exchanging parts of the hardware while other parts stay operative. This computing in time and space and many other fine grained adjustments within the architectures, opens new dimensions for electronic system design as well as for novel scheduling mechanisms based on well established graph-based algorithms in comparison to pure microprocessor based electronic systems. However, at the moment it is not possible to visualize the physical configuration of the chip and the manifold possibilities of manipulations on the device. This feature allows demonstrating the systems behavior and helps to debug final integrated reconfigurable systems. This paper presents an approach to the system integration of an autonomously working on-line visualization stand alone IP-Core integrated on Xilinx Virtex-II and Virtex-II Pro FPGAs

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

This paper introduces the first available tool flow for Dynamic Partial Reconfiguration on the Spartan-6 family. In addition, the paper proposes a new configuration method called Fast Start-up targeting modern FPGA architectures, where the FPGA is configured in two-steps, instead of using a single (monolithic) full device configuration. In this novel approach, only the timing-critical modules are loaded at power-up using the first high-priority bitstream, while the non-timing critical modules are loaded afterwards. This two-step or prioritized FPGA start-up is used in order to meet the extremely tight startup timing specifications found in many modern applications, like PCI-express or automotive applications. Finally, the developed tool flow and methods for Fast Start-up have been used and tested to implement a CAN-based automotive ECU on a Spartan-6 evaluation board (i.e., SP605). By using this novel approach, it was possible to decrease the initial bitstream size and hence, achieve a configuration time speed-up of up to 4.5×, when compared to a standard configuration solution.

REFLECT: Rendering FPGAs to Multi-core Embedded Computing

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.

Data Reallocation by Exploiting FPGA Configuration Mechanisms

Xilinx Virtex and Spartan FPGAs offer the possibility of dynamic and partial reconfiguration. This feature can be used in self-adaptive systems for providing the possibility to meet application requirements by exchanging parts of the hardware while other parts stay operative. The designer has to pay special attention to the communication wires connecting and crossing the reconfigurable areas. Module interfacing is still relatively complex, resource consuming and inflexible especially when regarding 2-dimensional reconfiguration approaches. In this paper a method is exploitet that overcomes these limitations achieved by using the reconfiguration interface not only for device configuration but also for data transfer between modules. In this paper we describe the approach in detail and present first implementation results.