Lars Kruse

Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs

In this paper, we present an approach for the calculation of lower and upper bounds on the power consumption of data path resources like functional units, registers, I/O ports, and busses from scheduled data flow graphs executing a specified input data stream. The low power allocation and binding problem is formulated. First, it is shown that this problem without constraining the number of resources can be relaxed to the bipartite weighted matching problem which is solvable in O(n) 3 . n is the number of arithmetic operations, variables, I/O-access or bus-access operations which have to be bound to data path resources. In a second step we demonstrate that the relaxation can be efficiently extended by including Lagrange multipliers in the problem formulation to handle a resource constraint. The estimated bounds take into account the effects of resource sharing. The technique can be used, for example, to prune the design space in high-level synthesis for low power before the allocation and binding of the resources. The application of the technique on benchmarks with real application input data shows the tightness of the bounds.

System level optimization and design space exploration for low power

We present a software tool for power dissipation analysis and optimization on the algorithmic abstraction level from C/C++ and VHDL descriptions. An analysis is most efficient on such a high level since the influence of design decisions on the power demand increases with increasing abstraction (A. Raghunathan et al., 1998). The ORINOCO/sup (R)/ tool enables us to compare different but functionally equivalent algorithms and bindings to RT-level architectures with respect to power consumption. The results of the optimized binding can be used to guide synthesis. In the experimental evaluation we compare the predicted optimization trend with synthesized implementations and prove the accuracy of our methodology and tool.

A new parameterizable power macro-model for datapath components

We propose a novel power macro-model which is based on the Hamming-distance of two consecutive input vectors and additional information on the module structure. The model is parameterizable in terms of input bit-widths and can be applied to a wide variety of datapath components. The good trade-off between estimation accuracy, model complexity and flexibility makes the model attractive for power analysis and optimization tasks on a high level of abstraction. Furthermore, a new approach is presented, that allows one to calculate the average Hamming-distance distribution of an input data stream. It is demonstrated, that the application of Hamming-distance distributions, instead of only average values, improves the estimation accuracy for a number of typical DSP-modules and data streams.

Power-simulation of cell based ASICs: accuracy-and performance trade-offs

Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level.

Power Macro-Modelling for Firm-Macro

An approach for power modelling of parameterized, technology independent design components (firm-macros) is presented. Executable simulation models in form of C++ classes are generated by a systematic procedure that is based on statistical modelling and table look-up techniques. In contrast to other table look-up based approaches the proposed model separately handles the inputs of a component, and with this it allows to model the effects of corresponding joint-dependencies. In addition, a technique for the generation of executable models is presented. The generated models are optimized with respect to simulation performance and can be applied for power analysis and optimization tasks on the behavioral and architectural level. Results are presented for a number of test cases which show the good quality of the model.

Lower and upper bounds an the switching activity in scheduled data flow graphs

In this paper we present an approach to calculate lower and upper bounds for the switching activity in scheduled data flow graphs. The technique can be used to prune the design space in high level synthesis for low power before allocation and binding of functional units and registers. The low power allocation and binding problem is formulated. It is shown that this problem can be relaxed to the bipartite weighted matching problem which is solvable in O(n/sup 3/) where n is the number of functional units or registers, respectively. The application of the technique on benchmarks shows the tightness of the bounds. Most of the investigated bounds were less than 1% off the minimum respectively maximum solutions.

Automatic nonlinear memory power modelling

Power estimation and optimization is an increasingly important issue in IC design. The memory subsystem is a significant aspect, since memory power can dominate total system power. Estimation and optimization hence rely heavily on models for embedded memories. We present an effective black box modelling methology for generating nonlinear memory models automatically. The resulting models are accurate, computationally modest, and in analytical form. They outperform linear models by far. Average absolute relative errors are below 6%.

Lower bounds on the power consumption in scheduled data flow graphs with resource constraints (poster paper)

The problem of estimating lower bounds on the power consumption in sc heduled data flow gr aphs with a fixed number of allocated r esources prior to binding is addressed. The estimated bound tak es into account the effects of r esource sharing. It is shown that by intr oducing Lagrangian multipliers and relaxing the low power binding problem to the Assignment Pr oblem, which can be solved in , a tight and fast computable bound is achievable. Experimental r esults show the good quality of the bound. In most cases, de viations smaller than 5% fr om the optimal binding wer observed. The pr oposed tec hnique can for e xample be applied in br anch and bound high-level synthesis algorithms for ef ficient pruning of the design space .

Lower bound estimation for low power high-level synthesis

This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. The estimated bound takes into account the effects of resource sharing. It is shown that by introducing Lagrangian multipliers and relaxing the low power binding problem to the Assignment Problem, which can be solved in O(n3), a tight and fast computable bound is achievable. Experimental results show the good quality of the bound. In most cases, deviations smaller than 5% from the optimal binding were observed. The proposed technique can for example be applied in branch and bound high-level synthesis algorithms for efficient pruning of the design space. The estimated lower bound can also be used as a starting point for low power binding heuristics to find optimal or near optimal binding solutions.