Wolfgang Nebel

Low power design in deep submicron electronics

1. Introduction -- 2. Application and Technology Forecast -- Future Low Power Applications -- Enabling Technologies -- Conclusions -- References -- 3. Low Power Design Flow and Libraries -- Key Issues on Libraries for Low Power Deep Sub-Micron Design -- Power Reduction Through Libraries -- Design Flow for Low Power Deep Sub-Micron -- Libraries for Low Power -- Conclusions -- References -- 4. Low Power Circuit and Logic Level Design -- 4.1. Modeling -- 4.2. Circuit and Logic Level Design -- 4.3. Power Estimation at the Logic Level -- 4.4. Advanced Power Estimation Techniques -- 5. Power Optimization -- 5.1. Layout Optimization -- 5.2. Combinational Circuit Optimization -- 5.3. Sequential Synthesis and Optimization for Low Power -- 5.4. RT and Algorithmic-Level Optimization for Low Power -- 5.5. High Level Synthesis for Low Power -- 6. System Level Low Power Design -- 6.1. Embedded System Design -- 6.2. Power Analysis and Design at System Level -- 6.3. Software Design for Low Power -- 7. Asynchronous Design -- 8. Low Voltage Technologies -- 9. Case Studies -- 9.1. Microprocessor Design -- 9.2. Low Power Applications at System Level.

System level optimization and design space exploration for low power

We present a software tool for power dissipation analysis and optimization on the algorithmic abstraction level from C/C++ and VHDL descriptions. An analysis is most efficient on such a high level since the influence of design decisions on the power demand increases with increasing abstraction (A. Raghunathan et al., 1998). The ORINOCO/sup (R)/ tool enables us to compare different but functionally equivalent algorithms and bindings to RT-level architectures with respect to power consumption. The results of the optimized binding can be used to guide synthesis. In the experimental evaluation we compare the predicted optimization trend with synthesized implementations and prove the accuracy of our methodology and tool.

Binding, Allocation and Floorplanning in Low Power High-Level Synthesis

This work is a contribution to high level synthesis for lowpower systems.While device feature size decreases, interconnectpower becomes a dominating factor.Thus it is importantthat accurate physical information is used during high-level synthesis.We propose a new power optimisation algorithm for RT-levelnetlists.The optimisation performs simultaneously slicing-treestructure-based floorplanning and functional unit binding andallocation.Since floorplanning, binding and allocation can use theinformation generated by the other step, the algorithm can greatlyoptimise the interconnect power.Compared to interconnect unawarepower optimised circuits, it shows that interconnect powercan be reduced by an average of 41.2%, while reducing overallpower by 24.1% on an average.The functional unit power remainsnearly unchanged.These optimisations are not achieved atthe expense of area.

Case study: system model of crane and embedded control

A case study of a crane is defined for the evaluation of system description languages. The plant (car and load) is given as a fourth-order linear system. The embedded control includes sensors, actuators, two control strategies, and diagnosis.

Inheritance concept for signals in object-oriented extensions to VHDL

Several proposals were made in the last few years to extend the hardware description language VHDL and to add mechanisms like inheritance from the object oriented domain to the language. This paper illuminates the principle problems arising when an inheritance concept for data types is added to VHDL. Solutions to these problems are proposed with an example of an inheritance mechanism for signals within an object-oriented extension to VHDL.

OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems

Dynamic Partial Reconfiguration (DPR) is a promising technology ready for use, enabling the design of more flexible and efficient systems. However, existing design flows for DPR are either low-level and complex or lack support for automatic synthesis. In this paper, we present a SystemC based modelling and synthesis flow using the OSSS+R framework for reconfigurable systems. Our approach addresses reconfiguration already on application level enabling early exploration and analysis of the effects of DPR. Moreover it also allows quick implementation of such systems using our automatic synthesis flow. We demonstrate our approach using an educational example.

A new parameterizable power macro-model for datapath components

We propose a novel power macro-model which is based on the Hamming-distance of two consecutive input vectors and additional information on the module structure. The model is parameterizable in terms of input bit-widths and can be applied to a wide variety of datapath components. The good trade-off between estimation accuracy, model complexity and flexibility makes the model attractive for power analysis and optimization tasks on a high level of abstraction. Furthermore, a new approach is presented, that allows one to calculate the average Hamming-distance distribution of an input data stream. It is demonstrated, that the application of Hamming-distance distributions, instead of only average values, improves the estimation accuracy for a number of typical DSP-modules and data streams.

The Lower Saxony research network design of environments for ageing: towards interdisciplinary research on information and communication technologies in ageing societies

Worldwide, ageing societies are bringing challenges for independent living and healthcare. Health-enabling technologies for pervasive healthcare and sensor-enhanced health information systems offer new opportunities for care. In order to identify, implement and assess such new information and communication technologies (ICT) the ‘Lower Saxony Research Network Design of Environments for Ageing’ (GAL) has been launched in 2008 as interdisciplinary research project. In this publication, we inform about the goals and structure of GAL, including first outcomes, as well as to discuss the potentials and possible barriers of such highly interdisciplinary research projects in the field of health-enabling technologies for pervasive healthcare. Although GALs high interdisciplinarity at the beginning slowed down the speed of research progress, we can now work on problems, which can hardly be solved by one or few disciplines alone. Interdisciplinary research projects on ICT in ageing societies are needed and recommended.

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.

Leakage in CMOS Circuits – An Introduction

In this tutorial, we give an introduction to the increasingly important effect of leakage in recent and upcoming technologies. The sources of leakage such as subthreshold leakage, gate leakage, pn-junction leakage and further GIDL, hot-carrier effect and punchthrough are identified and analyzed separately and also under PTV variations.