Laung-Terng Wang
Stanford University
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Publication
Featured researches published by Laung-Terng Wang.
vlsi test symposium | 2005
Xiaoqing Wen; Yoshiyuki Yamashita; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita
Research on low-power scan testing has been focused on the shift mode, with little or no consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR drop, resulting in significant yield loss. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0s and 1s to unspecified (X) bits in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes are obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
international test conference | 2005
Xiaoqing Wen; Yoshiyuki Yamashita; Shohei Morishima; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja; Kozo Kinoshita
Scan-based at-speed testing is a key technology to guarantee timing-related test quality in the deep submicron era. However, its applicability is being severely challenged since significant yield loss may occur from circuit malfunction due to excessive IR drop caused by high power dissipation when a test response is captured. This paper addresses this critical problem with a novel low-capture-power X-filling method of assigning 0s and 1s to unspecified (X) bits in a test cube obtained during ATPG. This method reduces the circuit switching activity in capture mode and can be easily incorporated into any test generation flow to achieve capture power reduction without any area, timing, or fault coverage impact. Test vectors generated with this practical method greatly improve the applicability of scan-based at-speed testing by reducing the risk of test yield loss
international test conference | 2004
Laung-Terng Wang; Xiaoqing Wen; Hiroshi Furukawa; Fei Sheng Hsu; Shyh Horng Lin; Sen Wei Tsai; Khader S. Abdel-Hafez; Shianling Wu
This work describes the VirtualScan technology for scan test cost reduction. Scan chains in a VirtualScan circuit are split into shorter ones and the gap between external scan ports and internal scan chains are bridged with a broadcaster and a compactor. Test patterns for a VirtualScan circuit are generated directly by one-pass VirtualScan ATPG, in which multi-capture clocking and maximum test compaction are supported. In addition, VirtualScan ATPG avoids unknown-value and aliasing effects algorithmically without adding any additional circuitry. The VirtualScan technology has achieved successful tape-outs of industrial chips and has been proven to be an efficient and easy-to-implement solution for scan test cost reduction.
vlsi test symposium | 2006
Xiaoqing Wen; Seiji Kajihara; Tatsuya Suzuki; Kewal K. Saluja; Laung-Terng Wang; Khader S. Abdel-Hafez; Kozo Kinoshita
High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1988
Laung-Terng Wang; Edward J. McCluskey
Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in each cone of logic driving a single output are guaranteed to be detected. Examples indicate that LFSRs based on cyclic codes have lower hardware cost and shorter or comparable test lengths than other approaches. These test-pattern generators are well suited to applications where short testing time, low hardware overhead, and 100% single-stuck-at fault coverage are required. >
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1988
Laung-Terng Wang; Edward J. McCluskey
Two hybrid schemes for the design of maximum-length sequence generators (MLSGs) are presented. Compared to an n-stage maximum-length LFSR (for generating 2/sup n/-1 nonzero distinct states) that uses m exclusive-or (XOR) gates, this hybrid MLSG will use exactly (m+1)/2 XOR gates if its characteristic polynomial meets certain requirements. For applications such as exhaustive testing, this hybrid MLSG is then reconfigured to include the all-zero state. It is shown that the reconfiguration is very simple and the hardware overhead is low. >
IEEE Transactions on Computers | 1986
Laung-Terng Wang
This paper presents a design technique for linear feedback shift registers that generate test patterns for pseudoexhaustive testing. This technique is applicable to any combinational network in which none of the outputs depends on all inputs. It does not rewire the original network inputs during in-circuit test pattern generation. Thus, the possibility of undetected faults on some inputs is eliminated.
international conference on computer design | 2006
Xiaoqing Wen; Tatsuya Suzuki; Yuta Yamato; Seiji Kajihara; Laung-Terng Wang; Kewal K. Saluja
X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effectiveness of previous X-filling methods suffers from lack of guidance in selecting targets and values for X-filling. This paper addresses this problem with a highly-guided X-filling method based on two novel concepts: (1) X-score for X-filling target selection and (2) probabilistic weighted capture transition count for Y-filling value selection. Experimental results show the superiority of the new X-filling method for capture power reduction.
IEEE Transactions on Computers | 1988
Laung-Terng Wang; Edward J. McCluskey
A design technique is given for linear-feedback shift registers (LFSR) that generate test patterns for pseudoexhaustive testing of networks with restricted output dependency. This technique is based on cyclic code theory. Examples indicate that LFSRs based on cyclic codes are easier to implement and have lower hardware overhead than LFSRs that use other linear codes. >
IEEE Design & Test of Computers | 2008
Laung-Terng Wang; Xiaoqing Wen; Shianling Wu; Zhigang Wang; Zhigang Jiang; Boryau Sheu; Xinli Gu
IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.