Wen-Ben Jone

Design theory and implementation for low-power segmented bus systems

The concept of bus segmentation has been proposed to minimize power consumption by reducing the switched capacitance on each bus [Chen et al. 1999]. This paper details the design theory and implementation issues of segmented bus systems. Based on a graph model and the Gomory-Hu cut-equivalent tree algorithm, a bus can be partitioned into several bus segments separated by pass transistors. Highly communicating devices are placed to adjacent bus segments, so most data communication can be achieved by switching a small portion of the bus segments. Thus, a significant amount of power consumption can be saved. It can be proved that the proposed bus partitioning method achieves an optimal solution. The concept of tree clustering is also proposed to merge bus segments for further power reduction. The design flow, which includes bus tree construction in the register-transfer level and bus segmentation cell placement and routing in the physical level, is discussed for design implementation. The technology has been applied to a μ-controller design, and simulation results by PowerMill show significant improvement in power consumption.

A dual-mode built-in self-test technique for capacitive MEMS devices

A dual-mode built-in self-test (BIST) scheme which partitions the fixed (instead of movable) capacitance plates of a capacitive microelectromechanical system (MEMS) device is proposed. The BIST technique divides the fixed capacitance plate(s) at each side of the movable microstructure into three portions: one for electrostatic activation and the other two equal portions for capacitance sensing. Due to such a partitioning method, the BIST technique can be applied to surface- and bulk-micromachined MEMS devices and other technologies. Further, the sensitivity and symmetry dual BIST modes based on this partitioning can also be developed. The combination of both BIST modes covers a larger defect set, so a more robust testing result for the device can be expected. The BIST technique is verified by three typical capacitive MEMS devices. Simulation results show that the proposed technique is an effective BIST solution for various capacitive MEMS devices.

Dynamic Characteristics of Power Gating During Mode Transition

With the technology moving into the deep sub-100-nm region, the increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes that with the latest and future technologies, power gating operates frequently in its transition mode, especially for aggressive leakage reduction. The dynamic characteristics of power gating during its mode transition is critical for making design decision. Hence we derive a fast, accurate, and temperature-aware model to characterize the dynamic behavior of power gating during mode transition. The applications of this model include the estimation of several key design parameters for power gating, such as dynamic virtual ground voltage, dynamic leakage variation and energy break-even time. It provides an efficient estimation engine for power gating design optimization. The accuracy of the model has been verified by extensive HSPICE experiments. The model is computationally efficient due to the usage of various approximation methods.

Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW

Run-time active leakage reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the energy aspect, for both power gating (PG) and reverse body bias (RBB) implementations.We develop two energy saving models for PG and RBB, respectively. These models can accurately estimate the circuit energy saving at any time, even when the circuit is in state transition. In PG modeling, we discover a physical phenomenon called ldquoinstant savingrdquo, which can affect the model accuracy by 30%-50%. Based on the RBB model, we derive the optimum design point of RBB for RALR. Finally in terms of energy saving, we define four figures-of-merit, to compare the efficacy of using PG and RBB to implement RALR.

Design and analysis of self-repairable MEMS accelerometer

In this paper, a self-repairable MEMS (SRMEMS) accelerometer design is proposed. The accelerometer consists of (n + m) identical modules: n of them serve as the main device, while the remaining m modules act as the redundancy. If any of the working module in the main device is found faulty, the control circuit will replace it with a good redundant module. In this way, the faulty device can be self-repaired through redundancy. The sensitivity loss due to device modularization can be well compensated by different design alternatives. The yield model for MEMS redundancy repair is developed. The simulation results show that the BISR (built-in self-repair) design leads to effective yield increase compared to nonBISR design, especially for a moderate nonBISR yield. By implementing the fault tolerance feature into MEMS devices, the yield as well as the reliability of a MEMS device implemented in a SoC can be improved.

Material Fatigue and Reliability of MEMS Accelerometers

MEMS (microelectromechanical system) reliability has been a very important issue, especially for safety-critical applications. Due to the diversity and multiple energy domains involved, MEMS devices are vulnerable to various failure mechanisms. MEMS reliability under different failure mechanisms should be analyzed separately. Since most of MEMS devices contain movable parts, material fatigue and aging under long-term repeated cycling load may lead to potential device failure, which in turn degrades the device reliability. In this paper, the reliability of poly-silicon MEMS comb accelerometers under material fatigue failure mechanism is analyzed. Based on ANSYS stress simulation, the mean-time-to-failure (MTTF) lifetimes and failure rates for both BISR (built-in self-repairable) and non-BISR poly-silicon MEMS comb accelerometers are derived. Simulation results show that the fatigue lifetime of MEMS accelerometers made by poly-silicon material can be good enough for general purpose applications. However, for some weak devices with certain structure defects, the material fatigue and aging may become potential threats. Compared to non-BISR design, BISR MEMS accelerometer demonstrates effective reliability improvement due to redundancy repair. MEMS reliability under material fatigue for other MEMS materials will be further studied in the future.

On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing

The design of space-efficient support hardware for built-in self-testing (BIST) is of great significance in the synthesis of present day very large scale integration (VLSI) circuits and systems, particularly in the context of design paradigm shift from system-on-board to system-on-chip (SOC). An approach to designing zeroaliasing space compaction hardware in relation to embedded cores-based SOC is proposed in this paper for single stuck-line faults, extending the well-known concepts of conventional switching theory, and of incompatibility relation to generate maximal compatibility classes (MCCs) using new graph theory concepts, based on optimal generalized sequence mergeability, as developed by the authors in earlier works. The paper briefly presents the mathematical basis of selection criteria for merger of an optimal number of outputs of the module under test (MUT) for realizing maximum compaction ratio in the design, along with some partial simulation results on ISCAS 85 combinational benchmark circuits, with programs ATALANTA and FSIM.

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

This paper describes a core-based test and diagnosis integration and automation system, called Turbo1500, which automatically synthesizes test and diagnosis logic in accordance with the IEEE 1500 standard. Turbo1500 serves two major purposes. One is for use as a core test automation tool in a system-on-chip (SOC) environment to automatically connect multiple cores from various sources and create testbenches each targeting an individual core under the control of a chip-level test access port (TAP) controller. The other is for hierarchical (block-by-block) core test and diagnosis when chips on a printed-circuit board are embedded with 1149.1 boundary scan I/O cells and cores under test and diagnosis are surrounded with 1500-compliant wrapper cells. Application experience showed that the simplicity of the IEEE 1500 standard combined with an easy-to-use automation tool can make core-based design for test and diagnosis no longer a nightmare, especially when some cores are extremely large or complex.

Crosstalk Test Pattern Generation for Dynamic Programmable Logic Arrays

Crosstalk noise is one of the major noise problems introduced by interconnect wire scaling and high clock speed. In modern deep submicrometer circuits (DSM), signal crosstalk can arise between two long parallel wires. Programmable logic arrays (PLAs) are important building blocks in digital very large scale integrated (VLSI) circuits; especially, dynamic PLAs have been used pervasively in modern high-speed circuit design because of their predictable delays. However, a dynamic PLA may suffer crosstalk noises that will cause the circuit to malfunction due to charge loss. In this paper, based on the characteristics of dynamic PLA crosstalk noise, an automatic test pattern generation (ATPG) method to detect the maximum crosstalk noise for each product line is presented. Test patterns are then compressed by a test pattern compressor. Experimental results obtained by simulating Microelectronics Center of North Carolina (MCNC) PLA benchmark circuits demonstrate the efficiency of the ATPG and test compression methods

Accurate energy breakeven time estimation for run-time power gating

Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been proposed as a critical figure of merit of RTPG. Our research introduces the definition of average EBT in a run-time environment. We develop a method to estimate the average EBT for any given circuit block, considering the impact of circuit states. HSPICE simulation results on ISCAS85 benchmark circuits show that the average EBT model has on the average 1.8% error. The CAD tool implemented based on the model can perform fast estimations with a speedup of 3000times over HSPICE.