Laurence E. Turner

Acceleration of finite-difference time-domain (FDTD) using graphics processor units (GPU)

The Finite-Difference Time-Domain (FDTD) method is used extensively in areas of microwave engineering and optics. However, FDTD runs too slow for some simulations to be practical, especially when run on standard desktop computers. The suitability of dedicated hardware for the acceleration of FDTD computations has been investigated. It is demonstrated that standard consumer Graphics Processor Units (GPUs) can be used to accelerate FDTD simulations by a factor of over seven, relative to an Intel CPU of similar technology generation. With OpenGL as the Application Programming Interface (API), a standard commercial graphics card has been programmed to solve a 2-D electromagnetic scattering problem.

Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method

The continuing advances in the field of electrical engineering, in areas like cellular communications, fiber optics, mobile and multi-gigahertz electronics have necessitated a computer-assisted design approach to the complex electromagnetic interactions and problems that arise. Finite-Difference Time-Domain (FDTD) Analysis is a very powerful tool for the modeling of electromagnetic phenomena. The algorithm is computationally intensive and simulations can run for a few hours to several days. Increasing the computation speed and decreasing the run times of this algorithm would bring greater productivity and new avenues of research to many facets of electrical engineering.The algorithm is transferred to custom FPGA-based hardware using a pipelined bit-serial arithmetic architecture. A one-dimensional resonator is used to verify the implementation and explore the hardware speed and costs. The computational speed is extremely fast and is not related to the number of computational cells in the simulation. Finally, a discussion of future research is presented.

Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm

The finite-difference time-domain (FDTD) algorithm has become a tool of choice in many areas of RF and microwave engineering and optics. However, FDTD runs too slow for some simulations to be practical, even when carried out on supercomputers. The development of dedicated hardware to accelerate FDTD computations has been investigated. In this paper, we demonstrate that off-the-shelf graphics processor units (GPUs) can be successfully used to accelerate FDTD simulations. Using C++, OpenGL, and several OpenGL extensions, a modern GPU has been programmed to solve a simple two dimensional electromagnetic scattering problem. The GPU outperforms a central processing unit (CPU) of comparable technology generation.

Design of digital filters using simulated annealing

A simulated annealing optimization algorithm is used in the design of finite impulse response (FIR) filters and fifth-order LDI all-pole digital filters. Using simulated annealing, sin(x)/x precompensating scheme based on both the FIR and LDI structures is presented. The design process begins with a random set of finite precision coefficients for the filter, making no attempt to obtain a good initial starting coefficient. The use of simulated annealing allows the use of nonclassical transfer functions in the design of digital filters, i.e. it allows for the design of arbitrary magnitude response filters.<<ETX>>

The analysis and implementation of digital filters using a special purpose CAD tool

The authors describe DIGICAP, a tool for use in the design and implementation of digital filters. DIGICAP will generate digital filter modules for the FIRST silicon compiler as well as digital filter subprograms to execute on general-purpose computers or special-purpose digital signal processors such as the TMS320 series. DIGICAP accepts as input a compact, high-level signal flow graph description of a digital filter. It allows the digital filter designer to rapidly evaluate the performance of different filter structures and implementation methods, including the effects of finite-precision arithmetic, and thus make structural and implementation choices that affect the critical constraints. The implementation of a particular second-order transfer function using three different recursive digital filter structures is considered as an example. >

Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs

Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT) processors are designed and implemented using a Xilinx Field Programmable Gate Array (FPGA) device XC 4010. This device allows a 16-point FFT/DCT processor implementation. To design the CLB-efficient FFT/DCT processor in FPGAs, a pipelined bit-serial architecture with bit-parallel input data format is employed. These processors operate with a 20 MHz bit-clock and 16-bit system word length, and compute an entire 16-point DFT/DCT transform for every 16-bit clock cycle.

BIT-Serial FIR Filters with CSD Coefficients for FPGAs

The implementation of finite impulse response (FIR) digital filters using pipelined bit-serial arithmetic and canonic signed digit (CSD) coefficient coding can be an effective use of hardware resources. However, the necessary time alignment of all data and control signals can be a tedious process. A methodology for implementing FIR filters using pipelined bit-serial arithmetic and field programmable gate arrays (FPGAs) is described.

Finite-difference time-domain method in custom hardware?

While the finite-difference time-domain (FDTD) method is very successful in electromagnetics, it is computationally intensive. Reducing the runtime of these simulations, by an order of magnitude or more, would greatly increase the productivity of FDTD users and open new avenues of research. A dedicated hardware implementation that accelerates FDTD computations could provide a means to attain that goal. As the first step, we have implemented a one- and two-dimensional FDTD method in hardware. The experiment proved that computational speed can be increased by as much as two orders of magnitude, and is independent of the number of cells in the simulation.

The design of peak constrained least squares FIR filters with low complexity finite precision coefficients

A method for the design of peak constrained least squares (PCLS) finite duration impulse response (FIR) digital filters with low complexity finite precision coefficients (FPC) based on Adams optimality criterion and an efficient local search is presented. Simple quantization of the infinite precision coefficients typically leads to filter designs which fail to meet the frequency response, passband to stopband energy ratio (PSR), and coefficient complexity (number of coefficient adders and subtracters) specifications. It is shown that it is possible to design a filter with an acceptable PSR that meets the frequency response specification while using a specified number of adders and subtracters.

Digital bilinear LDI ladder filters using lattice equivalents and wave concepts

Lossless discrete integrator (LDI)-based digital filters which implement bilinear transformed third- and sixth-order elliptic transfer functions are presented. The filters are designed by converting ladder prototypes to lattice prototypes, and realizing the resulting lattice impedance reflectances with LDI elements. The structures which result are amenable to compact biserial implementation and require only as many multiplication operations as the filter order. It is concluded that the lattice bilinear LDI formulation may be applicable to the design of parasitic insensitive switched-capacitor filters.<<ETX>>