Trevor W. Fox

A digital signal processing method for gene prediction with improved noise suppression

It has been observed that the protein-coding regions of DNA sequences exhibit period-three behaviour, which can be exploited to predict the location of coding regions within genes. Previously, discrete Fourier transform (DFT) and digital filter-based methods have been used for the identification of coding regions. However, these methods do not significantly suppress the noncoding regions in the DNA spectrum at. Consequently, a noncoding region may inadvertently be identified as a coding region. This paper introduces a new technique (a single digital filter operation followed by a quadratic window operation) that suppresses nearly all of the noncoding regions. The proposed method therefore improves the likelihood of correctly identifying coding regions in such genes.

The design of peak constrained least squares FIR filters with low complexity finite precision coefficients

A method for the design of peak constrained least squares (PCLS) finite duration impulse response (FIR) digital filters with low complexity finite precision coefficients (FPC) based on Adams optimality criterion and an efficient local search is presented. Simple quantization of the infinite precision coefficients typically leads to filter designs which fail to meet the frequency response, passband to stopband energy ratio (PSR), and coefficient complexity (number of coefficient adders and subtracters) specifications. It is shown that it is possible to design a filter with an acceptable PSR that meets the frequency response specification while using a specified number of adders and subtracters.

A methodology for rapid prototyping peak-constrained least-squares bit-serial finite impulse response filters in FPGAs

Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with a new application-specific mapping and placement method that uses JBits to avoid conventional general-purpose mapping and placement tools. JBits is a set of Java classes that provide an interface into the Xilinx Virtex FPGA configuration bitstream, allowing the user to generate new configuration bitstreams. PCLS coefficient generation allows passband-to-stopband energy ratio (PSR) performance to be traded for a reduction in the filters hardware cost without altering the minimum stopband attenuation. Fixed-point coefficients that meet the frequency response and hardware cost specifications can be generated with the PCLS method. It is not possible to meet these specifications solely by the quantization of floating-point coefficients generated in other methods.

A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM

A method for implementing bit-serial Finite Impulse Response (FIR) filters in Field Programmable Gate Arrays (FPGA) using JBits? to generate FPGA configuration bitstreams is presented. Traditional generalpurpose placement tools have been bypassed with a bit-serial FIR filter placement method that uses JBits to generate FPGA configuration bitstreams. The JBitsTM based bit-serial FIR filter placement method takes advantage of next-neighbor connectivity of bit-serial arithmetic cores to reduce the length of interconnections between cores and increase packing density of the cores in the FPGA. A design example for a filter with finite-precision coefficients generated by a Peak-Constrained Least-Squares filter design method is presented.

Rapid prototyping of field programmable gate array-based discrete cosine transform approximations

A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), quantization noise, hardware cost, and power consumption by optimizing the coefficient values and datapath wordlengths. Previous DCT design methods can only control the quality of the DCT approximation and estimates of the hardware cost by optimizing the coefficient values. It is shown that it is possible to rapidly prototype FPGA-based DCT approximations with near optimal coding gains that satisfy the MSE, hardware cost, quantization noise, and power consumption specifications.

Low coefficient complexity approximations of the one dimensional discrete cosine transform

A method for the design of arbitrarily exact Discrete Cosine Transform (DCT) approximations that permits perfect reconstruction using fixed point arithmetic is presented. Simple quantization of floating point precision coefficients typically leads to DCT approximations which fail to meet the coding gain, Mean Square Error (MSE), and coefficient complexity (number of coefficient adders and subtractors) specifications. It is shown that it is possible to design DCT approximations with near optimal coding gains that meets the MSE and coefficient complexity requirements. Finite precision effects are discussed for these DCT approximations.

Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA

A method for the design of low-cost near-exact Discrete Cosine Transform (DCT) approximations on the Xilinx Virtex FPGA is presented. This method can be used to control the coding gain, Mean Square Error (MSE), quantization noise, hardware cost, and power consumption of the DCT approximation. The Xilinx Place-And-Route (PAR) process and XPWR are used to gauge the hardware cost and the power consumption respectively. It is shown that it is possible to generate FPGA based DCT approximations with near optimal coding gains that meet the Mean Square Error (MSE), hardware cost, quantization noise, and power consumption requirements.

Transmit and receive digital filters subject to hardware cost constraints

A method for the design of field programmable gate array (FPGA) based bit-serial Finite duration impulse response (FIR) transmit and receive digital filters is presented. Transmit and receive digital filters can be designed with near zero inter-symbol interference (ISI) and a specified normalized minimum stopband attenuation while using a specified number of logic elements (LEs). A tradeoff between the ISI and the hardware cost (the number of required LEs) is explored. It is shown that it is possible to obtain low cost transmit and receive digital filters at the expense of higher ISI.

The Multiplier Tree FIR filter architecture

The Multiplier Tree FIR filter architecture eliminates redundant arithmetic elements in the constant coefficient multipliers of the transposed form FIR filter architecture, facilitating low hardware cost filter implementations. This paper presents the Multiplier Tree FIR Filter architecture and implementation results for this architecture. A comparison of this architecture to previous FIR filter implementations is presented. Results for 95 and 45-tap FIR filter implementations show hardware cost can be reduced significantly with the Multiplier Tree architecture.

A method of implementing bit-serial LDI ladder filters in FPGAs using JBits

A simulated annealing design method for low hardware cost bit-serial Lossless Discrete Integrator (LDI) recursive digital filter implementations using Field Programmable Gate Arrays (FPGAs) with JBits/spl trade/ is presented. This method jointly minimizes the magnitude frequency response error and the filter hardware cost. The next-neighbor connectivity of bit-serial systems is exploited to create a placement method using JBits/spl trade/ to avoid time-consuming general-purpose placement tools for FPGAs in addition to the hardware cost reduction benefits of bit-serial architectures. A design example using the proposed method is presented in which a 30.2 percent hardware cost reduction is obtained.