Laurent Latorre

Low-cost phase noise testing of complex RF ICs using standard digital ATE

This paper introduces a low-cost technique for phase noise testing of complex RF devices. The technique is based on the acquisition of the signal delivered on the IF output by a standard digital Automated Test Equipment (ATE). A dedicated digital processing algorithm is proposed that permits to achieve phase noise evaluation from the captured binary data. An experimental setup is developed to validate the proposed technique and measurements on actual analog signals demonstrate a very good agreement with conventional phase noise measurements.

On the use of standard digital ATE for the analysis of RF signals

In this paper, we investigate the use of standard digital ATE for the analysis of FM-modulated RF signals. The key idea is to use the 1-bit digitizer of a digital test channel in order to convert the frequency information contained in a FM-modulated signal into a timing information contained in a digital bit stream; a post-processing algorithm based on the concept of zero-crossing detection is then employed to retrieve this information. Coherent under-sampling is exploited to extend the capabilities of test equipment with a limited sampling frequency for the analysis of high-frequency signals. The proposed approach is evaluated on two different case studies related to LTE and GSM communication standards. Both simulation and hardware experiments are presented to demonstrate the viability of the technique.

Rejection of power supply noise in wheatstone bridges: Application to piezoresistive MEMS

This paper deals with the design of MEMS using piezoresistivity as transduction principle. It is demonstrated that when the sensor topology doesnpsilat allow a perfect matching of strain gauges, the resolution is limited by the ability of the conditioning circuit (typically a Wheatstone bridge) to reject power supply noise. As this ability is strongly reduced when an offset voltage is present at the output of the bridge, the proposed architecture implements a feedback loop to control MOS transistors inserted in the Wheatstone bridge to compensate resistor mismatches. This feedback exhibits a very good offset cancellation and therefore a better resolution is achieved.

A CMOS-MEMS Inertial Measurement Unit

This paper introduces the first monolithic integration of a 3-axis accelerometer, a 2-axis magnetometer and a full-custom front-end electronics. This complete Inertial Measurement Unit (IMU) has been designed on a single die of 7.5mm2 in a 0.35°m CMOS technology. The five electromechanical sensors are batch-manufactured using a single-step wet etching of the CMOS die. Compared to existing Inertial Measurement Units, assembly costs and common issues associated with sensor misalignments are suppressed. Sensors make use of resistive transduction, either mechanically or thermally induced. The on-chip electronic has been designed to cancel parasitic effects such as offset and to optimize the signal-to-noise ratio on each measurement axis. The achieved performance (8-bits on Earth magnetic field measurement, 8-bits and 6-bits on x/y and z gravity acceleration respectively) makes the device suitable for numerous applications in consumer electronics.

A wide-bandwidth, wide dynamic-range thermal ΣΔ architecture for convective accelerometers

This work describes the implementation and the modeling of a convective accelerometer with 1st-order thermal ΣΔ readout. This closed-loop system is obtained by the hybrid combination of a CMOS sensor prototype which includes an amplifier, and discrete electronic devices. A high comparator precision is reached by dynamic offset cancellation of the amplifier. After a modeling of the Johnson noise and of the quantization-noise, the parameters of the modulator are optimized to get a good linearity, an improved gain precision and a wide dynamic range.

Design of a micromachined CMOS compass

This paper presents the design of a low-cost monolithic CMOS microcompass. The system is based on a cantilever actuated by the Lorenz force. Conditioning circuitry has been designed carefully to reject noise, to eliminate parasitic phenomena such as thermal effects, and to be robust to process scatterings without the need of an external trimming. Mixed-mode simulations have been enabled using a behavioral description of the sensor, and validations of the complete system have been performed. The expected performance has a resolution inferior to 1/spl deg/ for a total surface of 10.6mm/sup 2/ and a power consumption of 56mW (without the digital processing bloc).

Phase noise measurement on IF analog signals using standard digital ATE resources

This paper introduces a low-cost technique for phase noise measurement on IF analog signals. The technique is based on signal acquisition from a digital Automated Test Equipment (ATE) and a dedicated post-processing algorithm that permits to reconstruct the time-domain phase of the IF analog signal from the digital capture. An experimental setup is developed to validate the proposed technique and measurements on actual analog signals demonstrate a very good agreement with conventional phase noise measurements.

Level-crossing based QAM demodulation for low-cost analog/RF testing

This paper concerns production test of analog and RF communication devices. The use of standard digital tester channel for the acquisition of modulated analog/RF signals is investigated in order to implement low-cost functional test. The idea is to use the comparator available in a standard digital test resource to record level-crossing events on a signal coming from the device under test, and then to apply a dedicated algorithm to retrieve the signal information. The proposed method is evaluated through both simulation and hardware experiments using the popular QAM coding scheme that combines both amplitude and phase shift-keying. The approach is generic and can be applied to a broad range of modulation schemes.

A micro-power high-resolution ΣΔ CMOS temperature sensor

This paper introduces a simple and compact CMOS temperature sensor which sensing principle relies on the measurement of integrated polysilicon resistances. The architecture makes use of two resistive layers of opposite temperature coefficients, both being available in the CMOS process. In order to tackle power consumption issues, usually related to resistive transduction and Wheatstone bridge conditioners, resistors are here placed in an original stage featuring gain even at very low-biasing current (2µA in this case). This analog front-end is used into a 1st order ΣΔ modulator, providing a digital output (i.e. a bitstream) with little additional silicon surface. The paper describes the design of the circuit and provides both simulation and experimental results. Experimental data are obtained from silicon prototypes, over a - 40°C to 100°C temperature range. High resolution (below 0.1°C) is observed.

AM-demodulation of analog/RF signals using digital tester channels

This paper investigates a signal acquisition protocol based on level-crossings that permits the demodulation of AM analog/RF signals using only standard digital ATE. The fundamental concept is to capture the signal through the 1-bit comparator available in digital tester channels and to process the resulting bit stream to retrieve the analog/RF signal characteristics. The proposed solution is evaluated through both simulation and hardware experiments.