Florence Azaïs

Characterization of the transient behavior of gated/STI diodes and their associated BJT in the CDM time domain

A measurement setup for the characterization of very fast transient responses in the CDM time domain is described in this paper. Experimental results are demonstrated on STI and gated diodes with a guard ring in a 65 nm and 130 nm CMOS technology. The superior behavior of gated diodes during triggering is highlighted.

Smart selection of indirect parameters for DC-based alternate RF IC testing

In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.

Making predictive analog/RF alternate test strategy independent of training set size

This paper presents an alternate test implementation based on model redundancy that permits to achieve lower prediction errors than a classical implementation, even if training is performed over a small set of devices. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may apply. The approach is illustrated on a real case study that employs production test data from an RF power amplifier. Results show that, on the contrary to the classical implementation where prediction accuracy degrades when reducing the training set size, the proposed approach permits to preserve prediction accuracy independently of the training set size, while only a very small number of devices are directed to the second tier of the test flow.

Boolean and current detection of MOS transistor with gate oxide short

We study the voltage and current behavior of Gate Oxide Short faults due to pinholes in the gate oxide. Our objective is to give a detailed analysis of the behavior of the GOS defect taking into account random parameters such as the GOS resistance, the GOS location and the GOS size. To facilitate an accurate analysis, we use a bi-dimensional array, and, since a complete analysis is desired, we derive characteristics of the GOS as a function of its resistance, location and size. Finally, we validate the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.

Modeling the influence of etching defects on the sensitivity of MEMS convective accelerometers

In this paper, a behavioral model that includes the influence of etching defects on the sensitivity of MEMS convective accelerometers is presented. Starting from an existing behavioral model, new physically-based expressions have been derived to introduce etching defects in the simulation of thermal conduction in the sensor. In addition, a semi-empirical model has been introduced for thermal convection. Finally, a very good agreement is obtained between the behavioral model and FEM simulations.

Investigations on electrical-only test setup for MEMS convective accelerometer

In this paper, we investigate potential solutions for the development of an electrical-only test procedure for MEMS convective accelerometers. The objective is to define an alternative low-cost test procedure applicable at wafer-level. Simple electrical test measurements are analyzed and a behavioral model allowing fault injection is developed. Simulation results show that most of the parametric faults that affect the device specifications can be detected with electrical measurements. Only faults that affect the convective behavior escape this alternative test. A preliminary study of convective effects using FEM simulation is then conducted to identify the key parameters that should be included in the model for the subsequent definition of adequate electrical test parameters.

An electrical test method for MEMS convective accelerometers: Development and evaluation

In this paper, an alternative test method for MEMS convective accelerometers is presented. It is first demonstrated that device sensitivity can be determined without the use of physical test stimuli by simple electrical measurements. Using a previously developed behavioral model that allows efficient Monte-Carlo simulations, we have established a good correlation between electrical test parameters and device sensitivity. Proposed test method is finally evaluated for different strategies that privilege yield, fault coverage or test efficiency.

A new multi-finger SCR-based structure for efficient on-chip ESD protection

This paper introduces a new SCR-based (silicon controlled rectifier) structure for on-chip ESD protection. The STMSCR (smart triggered multi-finger SCR) relies on the bimodal operation of a LSCR (lateral SCR) using an external triggering circuitry that permits switching from a transparency mode to a protection mode as soon as an ESD event is detected. The trigger voltage can be adjusted by design without any impact on the ESD performance. The STMSCR is multi-finger compliant, thus allowing area-efficient design of pad-located ESD protection. The STMSCR is demonstrated in a 0.18 μm CMOS technology without any process customization; an HBM failure threshold over 115 V/μm is reached while always ensuring current uniformity in multi-finger structures.

Low-cost phase noise testing of complex RF ICs using standard digital ATE

This paper introduces a low-cost technique for phase noise testing of complex RF devices. The technique is based on the acquisition of the signal delivered on the IF output by a standard digital Automated Test Equipment (ATE). A dedicated digital processing algorithm is proposed that permits to achieve phase noise evaluation from the captured binary data. An experimental setup is developed to validate the proposed technique and measurements on actual analog signals demonstrate a very good agreement with conventional phase noise measurements.

On the use of standard digital ATE for the analysis of RF signals

In this paper, we investigate the use of standard digital ATE for the analysis of FM-modulated RF signals. The key idea is to use the 1-bit digitizer of a digital test channel in order to convert the frequency information contained in a FM-modulated signal into a timing information contained in a digital bit stream; a post-processing algorithm based on the concept of zero-crossing detection is then employed to retrieve this information. Coherent under-sampling is exploited to extend the capabilities of test equipment with a limited sampling frequency for the analysis of high-frequency signals. The proposed approach is evaluated on two different case studies related to LTE and GSM communication standards. Both simulation and hardware experiments are presented to demonstrate the viability of the technique.