Laurent Lemarchand

A two-step optimization technique for functions placement, partitioning, and priority assignment in distributed systems

Modern development methodologies from the industry and the academia for complex real-time systems define a stage in which application functions are deployed onto an execution platform. The deployment consists of the placement of functions on a distributed network of nodes, the partitioning of functions in tasks and the scheduling of tasks and messages. None of the existing optimization techniques deal with the three stages of the deployment problem at the same time. In this paper, we present a staged approach towards the efficient deployment of real-time functions based on genetic algorithms and mixed integer linear programming techniques. Application to case studies shows the applicability of the method to industry-size systems and the quality of the obtained solutions when compared to the true optimum for small size examples.

iFogStor: An IoT Data Placement Strategy for Fog Infrastructure

Internet of Things (IoT) will be one of the driving application for digital data generation in the next years as more than 50 billions of objects will be connected by 2020. IoT data can be processed and used by different devices spread all over the network. The traditional way of centralizing data processing in the Cloud can hardly scale because it cannot satisfy many of the latency critical IoT applications. In addition, it generates a too high network traffic when the number of objects and services increase. Fog infrastructure provides a beginning of an answer to such an issue. In this paper, we present a data placement strategy for Fog infrastructures called iFogStor. The objective of iFogStor is to take profit of the heterogeneity and location of Fog nodes to reduce the overall latency of storing and retrieving data in a Fog. We formulated the data placement problem as a Generalized Assignment Problem (GAP) and proposed two ways to solve it: 1) an exact solution using integer programming and 2) a heuristic one based on geographical zoning to reduce the solving time. Both solutions proved very good performance as they reduced the latency by more than 86% as compared to a Cloud based solution and by 60% as compared to a naive Fog solution. Using geographical zoning heuristic can allow solving problems with large number of Fog nodes efficiently and in a couple of seconds making iFogStor feasible in runtime and scalable.

Architecture Exploration of Real-Time Systems Based on Multi-objective Optimization

This article deals with real-time embedded system design and verification. Real-time embedded systems are frequently designed according to multi-tasking architectures that have timing constraints to meet. The design of real-time embedded systems expressed as a set of tasks raises a major challenge since designers have to decide how functions of the system must be assigned to tasks. Assigning each function to a different task will result in a high number of tasks, and then in higher preemption overhead. In contrast, mapping many functions on a limited number of tasks leads to a less flexible design which is more expensive to change when the functions of the system evolve. This article presents a method based on an optimization technique to investigate the assignment of functions to tasks. We propose a multi-objective evolution strategy formulation which both minimizes the number of preemptions and maximizes task laxities. Our method allows designers to explore the search space of all possible function to task assignments and to find good tradeoffs between the two optimization objectives among schedulable solutions. After explaining our mapping approach, we present a set of experiments which demonstrates its effectiveness for different system sizes.

A Computational Comparison of Different Algorithms for Very Large \(p\)-median Problems

In this paper, we propose a new method for solving large scale (p)-median problem instances based on real data. We compare different approaches in terms of runtime, memory footprint and quality of solutions obtained. In order to test the different methods on real data, we introduce a new benchmark for the (p)-median problem based on real Swedish data. Because of the size of the problem addressed, up to 1938 candidate nodes, a number of algorithms, both exact and heuristic, are considered. We also propose an improved hybrid version of a genetic algorithm called impGA. Experiments show that impGA behaves as well as other methods for the standard set of medium-size problems taken from Beasley’s benchmark, but produces comparatively good results in terms of quality, runtime and memory footprint on our specific benchmark based on real Swedish data.

MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management

Flash memories based storage systems have some specific constraints leading designers to encapsulate some management services into a hardware/software layer called the Flash Translation Layer (FTL). The performance of flash based storage systems such as Solid State Drives (SSDs) are strongly driven by the FTL intricacies and also by a cache system placed on top of the FTL. Those systems are generally developed independently. In order to accelerate I/O request processing, FTLs use some space of the flash memory called the over-provisioning space. The over-provisioning space is thus not dedicated to data storage and should be small and of fixed size. This paper presents MaCACH, a maximum page-mapped region usage, cache-aware, and configurable hybrid mapping scheme. MaCACH design is based on two motivations: (1) the FTL should make full profit of the fixed size over-provisioning space to accelerate I/O processing, (2) as in most cases cache systems are put on top of FTLs, the latter should use information about the former in order to optimize data management. MaCACH is mainly based on two solutions: (1) it uses a proportional–integral–derivative (PID) feedback control system to keep the over-provisioning space fully used whatever the I/O workload characteristics, making it more efficient, (2) it is cache-aware as it uses a common feature of flash specific caches in order to route evicted data toward a page-mapped or block-mapped area which helps in optimizing the write operation costs. The performance evaluation shows very good behavior of MaCACH as compared to state-of-the-art FTLs in addition to a high flexibility as MaCACH has a large configuration space.

Modeling the Geometry of the Endoplasmic Reticulum Network

We have studied the network geometry of the endoplasmic reticulum by means of graph theoretical and integer programming models. The purpose is to represent this structure as close as possible by a class of finite, undirected and connected graphs the nodes of which have to be either of degree three or at most of degree three. We determine plane graphs of minimal total edge length satisfying degree and angle constraints, and we show that the optimal graphs are close to the ER network geometry. Basically, two procedures are formulated to solve the optimization problem: a binary linear program, that iteratively constructs an optimal solution, and a linear program, that iteratively exploits additional cutting planes from different families to accelerate the solution process. All formulations have been implemented and tested on a series of real-life and randomly generated cases. The cutting plane approach turns out to be particularly efficient for the real-life testcases, since it outperforms the pure integer programming approach by a factor of at least 10.

Parallel Synthesis of Large Combinational Circuits for FPGAs

Reconfigurable circuits such as F P G A s become much larger, reaching the 100.000 gates, and are a credible alternative for some computation intensive applications. However, to be accepted, very important progresses must be achieved in the programming methods, since several bottlenecks limit the design process for FPGA. Generating a circuit from an high level specification involves numerous tasks. The goal of the logic synthesis task is to improve the circuit on criteria such as speed or area, and to take technology constraints into accounL The aim of our work is to speed up this phase, since it involves important runtime and huge memory requirements, even if heuristics are used.

An object-oriented environment for specification and concurrent execution of genetic algorithms

Genetic algorithms (GA) mimic natural reproduction to search for complex problem solutions. Their principles are shortly explained. A point of interest is the regular and repetititve structure of computation involving communication, data exchanges, and control phases. Interaction with presentation and analysis tools is also a requirement. This make sense for the definition of a general framework allowing fast building of parallel applications in an object-oriented system. A GA workbench is developed using the Smalltalk-80 system with parallel machine code generation in mind.

Multi-objective design exploration approach for Ravenscar real-time systems

This article deals with the design exploration and verification of real-time critical systems. Assigning the functions to the tasks of the target real-time operating system is a part of the design process. Finding a suitable design involves many important design decisions that have a strong impact on the system quality criteria. However, with the increasing complexity and scale of today’s systems and the large number of possible design solutions, making design decisions while balancing conflicting quality criteria becomes error-prone and unmanageable for designers. We propose an automated method using a multi-objective evolutionary algorithm guided by an architectural clustering technique. This method allows designers to search the design space for schedulable solutions with respect to multiple competing performance criteria. To assess our method, several evaluations were performed. One of them shows that we were able to produce the exact optimal solution sets for