Laurent Pain

Electron beam direct write lithography flexibility for ASIC manufacturing: an opportunity for cost reduction (Keynote Paper)

With the strong increase of mask complexity and associated price for each new technology node, mask less lithography represents more and more an interesting and complementary alternative for ASIC manufacturing especially in the fields of low volume and leading eadge technology applications. In the semiconductor business where prices and cycle time are constantly pressured, the capability and flexibility of the electron beam direct write offer an effective real cost and cycle time opportunity thanks to its high-resolution capability but also to its ability to print, modify or correct design everywhere in a circuit. This paper highlights application examples where the advantages of this lithography solution are demonstrated for advanced research and development application with the patterning of 45 nm SRAM and for the fast validation of architecture designs. This work confirms that mask less lithography can be transparently placed into production environment, in association with the golden optical lithography reference.

New electron beam proximity effects correction (EBPC) approach for 45nm and 32nm nodes

Summary form only given. After the last successful results obtained these last years, EBDW (E-beam direct write) use for ASIC manufacturing is now demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle product and advanced R&D applications. In this way, the development of the process needs a good dimensional control of patterns. That means a better control of the proximity effects affected by the back scattering electrons and others phenomenon. There exist several methods to provide a correction for these effects and the most commonly used is that of dose adjustment as implemented by PDF solutions PROXECCO software package. However it has been observed that this correction is not perfect and significantly it fails to accurately correct the smallest and most dense structures encountered in designs with features below 65nm. To continue reducing feature sizes a method to provide a complementary correction to PROXECCO has been proposed. Based upon detailed characterization of the observed effects a rules correction scheme has been developed not dissimilar to the rule based corrections used in optical proximity correction (OPC). This electron beam proximity correction, or EBPC, has been shown to provide good results down to 40nm, with improvements in CD linearity, the isolated dense bias (IDB), line end shortening (LES), mask error enhancement factor (MEEF) and the energy latitude (EL) all of which leads to an improvement in the overall accuracy of the design, and furthermore an improvement in the process window.

65 nm device manufacture using shaped E-Beam lithography

In this paper, SRAM cell device manufacture using shaped electron beam lithography was developed. TEM view of SRAM cell was showed.

Determination of spot size and acid diffusion length in positive chemically amplified resist for e-beam lithography at 100 and 5 kV

An experimental method to determine the beam spot size and the acid diffusion length of a positive chemically amplified electron-beam resist (p-CAR) is proposed. This method is applied to a reference p-CAR with a Vistec VB6 electron beam at 100 kV and with a MAPPER tool at 5 kV. Beam spot size characterization is based on the width measurement of a single line exposure. This procedure is applied to two specific dose ranges. In the first one, the chemical mechanism occurring in the exposed resist is dominated by acid catalytic deprotection of a partially protected polymer (standard process). In the second dose range, the chemistry is governed by the cross-linking mechanism due to the intentional overdose of the p-CAR, leading to a polarity inversion. The authors assume that comparing the results obtained with the standard and the cross-linked p-CAR enables the determination of the acid diffusion length of the p-CAR process. This hypothesis was verified with measurements performed with a nonchemically ampli...

Ultimate lithographic performances of advanced resists CAR or non-CAR resist?

In a period where industry strongly struggles to find a cost effective alternative solution to the 193nm double patterning strategy, resist manufacturers actively started to design new resist platforms for the future lithography candidates such as EUV or multi-beam. Chemically amplified resists proved their efficiency until now to reach resolution requirements and simultaneously keeping sensitivity target. Below 20nm, edge roughness starts to play an important role on patterning quality and critical dimension control. Simultaneously non CAR resist are showing attracting resolution progress with reasonable sensitivity levels. In the frame of the multi-beam program IMAGINE, performances of advanced resist platforms have been evaluated at various accelerating voltage: 5kV on the MAPPER multi-beam platform and at 100kV on a VISTEC Gaussian tool. This paper reports on the comparison results obtained on those two types of chemistry schemes in terms of resolution, sensitivity and roughness.

Shaped e-beam lithography integration work for advanced ASIC manufacturing: progress report

For the sub-90 nm node integrated circuits design rules, ITRS forecasts require minimal gate line width down to 55-35 nm. To reach such aggressive targets, most advanced optical lithography tools combined with all reticle enhancement techniques will be requested inducing important manufacturing cost and mask cycle time increase. In order to address prototyping market and reduce fabrication cost, shaped electron beam lithography may represent a technological alternative for cost reduction due to its high resolution and potential throughput capabilities. This paper is focused on the integration of this technology in standard ASIC plant, including resist process and overlay capabilities.

Manufacturing concerns for advanced CMOS circuit realization EBDW alternative solution for cost and cycle time reductions

The introduction of Electron Beam Direct Write lithography into production represents a challenging alternative to reduce cost and cycle time increase induced by the introduction of new generation nodes. This paper details the development work performed to insert transparently direct write lithography process and alignment strategies into CMOS process flows. Finally, this interchangeability between E-Beam and optical lithography steps offers a complete flexibility for device architecture validation and allowed the development of a complete low cost 65nm platform including low-power and general-purpose applications.

Advanced patterning studies using shaped e-beam lithography for 65-nm CMOS preproduction

With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.

Comparison of EUV and e-beam lithographic technologies for sub-22-nm node patterning

Prompted by the fact that the International Technology Roadmap for Semiconductors (ITRS) has declared no proven optical solutions are available for sub 22nm hp patterning, we have investigated e-Beam and Extreme Ultraviolet (EUV) resist performance with a view to High Volume Manufacturing (HVM) at these design rules. Since these patterning technologies are considered the leading candidates to replace Immersion ArF (ArFi) multilevel patterning schemes, it was deemed prudent to assess the readiness of these imaging options. We review the advantages and disadvantages of each patterning method and highlight general technology challenges as well as resist specific challenges. In terms of resist specific challenges, we primarily focus on Resolution, Linewidth roughness and Sensitivity (RLS) tradeoffs for both e-Beam and EUV patterning. These metrics are of particular relevance as the industry continues to contend with the well known tradeoffs between these performance criteria. The RLS relationship is probed for both line space and contact hole patterns with each exposure wavelength. In terms of resist selection, we focus on our advanced Polymer Bound PAG (PBP) resist platform as it has been designed for high resolution applications. We also assess resist outgassing during EUV exposure as it is a potential barrier to adoption of EUV for HVM.

Electron beam direct write: shaped beam overcomes resolution concerns

In semiconductor industry time to market is one of the key success factors. Therefore fast prototyping and low-volume production will become extremely important for developing process technologies that are well ahead of the current technological level. Electron Beam Lithography has been launched for industrial use as a direct write technology for these types of applications. However, limited throughput rates and high tool complexity have been seen as the major concerns restricting the industrial use of this technology. Nowadays this begins to change. Variable Shaped Beam (VSB) writers have been established in Electron Beam Direct Write (EBDW) on Si or GaAs. In the paper semiconductor industry requirements to EBDW will be outlined. Behind this background the Vistec SB3050 lithography system will be reviewed. The achieved resolution enhancement of the VSB system down to the 22nm node exposure capability will be discussed in detail; application examples will be given. Combining EBDW in a Mix and Match technology with optical lithography is one way to utilize the high flexibility advantage of this technology and to overcome existing throughput concerns. However, to some extend a common Single Electron Beam Technology (SBT) will always be limited in throughput. Therefore Vistecs approach of a system that is based on the massive parallelisation of beams (MBT), which was initially pursued in a European Project, will also be discussed.