Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Lawrence G. Pearce is active.

Publication


Featured researches published by Lawrence G. Pearce.


international integrated reliability workshop | 1994

Investigation of plasma process damage in a thick gate oxide, large geometry, process using protected devices

M.J. Dion; John J. Hackenberg; Donald F. Hemmenway; Lawrence G. Pearce; J.W. Werner

Plasma process induced damage is a major device issue. A non-uniform plasma can generate significant MOS gate damage and this damage is commonly reported on state-of-the-art thin oxides and small devices. This work will describe plasma damage observed on a thick gate, large geometry process. Protected devices were used to confirm plasma damage. Protected devices for study of damage along with issues with fuse protection are discussed. Blowing of fuses may be better than laser cutting and fuse protection of all device nodes may not be needed.


Archive | 1996

Monolithic class D amplifier

Lawrence G. Pearce; Donald F. Hemmenway


Archive | 1995

High efficiency quasi-vertical DMOS in CMOS or BICMOS process

Lawrence G. Pearce


Archive | 1996

Late process method and apparatus for trench isolation

Donald F. Hemmenway; Lawrence G. Pearce


Archive | 1995

Pilot transistor for quasi-vertical DMOS device

Lawrence G. Pearce


Archive | 1988

Technique for forming planarized gate structure

Richard L. Lichtel; Lawrence G. Pearce; Dryer A. Matlock


Archive | 1996

Late process method for trench isolation

Donald F. Hemmenway; Lawrence G. Pearce


Archive | 2003

BiCMOS process with low temperature coefficient resistor (TCRL)

Donald F. Hemmenway; Jose Avelino Delgado; John D. Butler; Anthony L. Rivoli; Michael David Church; George V. Rouse; Lawrence G. Pearce; George Bajor


Archive | 1987

Technique for elimination of polysilicon stringers in direct moat field oxide structure

Dyer A. Matlock; Richard L. Lichtel; Lawrence G. Pearce


Archive | 1987

CMOS device having reduced spacing between N and P channel

Kenneth K. O; Lawrence G. Pearce; Dyer A. Matlock

Collaboration


Dive into the Lawrence G. Pearce's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge