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Dive into the research topics where John J. Hackenberg is active.

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Featured researches published by John J. Hackenberg.


symposium on vlsi technology | 2006

1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

Paul A. Grudowski; Vance H. Adams; Xiang-Zheng Bo; Konstantin V. Loiko; Stan Filipiak; John J. Hackenberg; Mohamad M. Jahanbani; M. Azrak; S. Goktepeli; M. Shroff; Wen-Jya Liang; S.J. Lian; V. Kolagunta; N. Cave; Chi-Hsi Wu; M. Foisy; H.C. Tuan; Jon Cheek

We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary


international soi conference | 2006

Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

Xiangzheng Bo; Paul A. Grudowski; Vance H. Adams; Konstantin V. Loiko; Daniel Tekleab; Stan Filipiak; John J. Hackenberg; Venkat R. Kolagunta; Mark C. Foisy; Li-te Lin; K.h. Fung; Chi-hsi Wu; Hsiao-chin Tuan; Jon Cheek

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations


Proceedings of SPIE | 2007

Improved dimension and shape metrology with versatile atomic force microscopy

Mark Caldwell; Tianming Bao; John J. Hackenberg; Brian McLain; Omar Munoz; Tab A. Stephens; Victor H. Vartanian

Accurate, precise, and rapid three-dimensional (3D) characterization of patterning processes in integrated circuit development and manufacturing is critical for successful volume production. As process tolerances and circuit geometries shrink with each technology node, the precision, accuracy, and capability requirements for dimension and profile metrology intensify. The present work adopts the scanning probe based technology, 3D atomic force microscopy (AFM), to address current and next-generation critical dimension (CD) metrology needs for device features at a variety of process steps. Fast, direct, and non-destructive 3D profile characterization of patterning processes is a primary benefit of CD AFM metrology. The CD AFM utilizes a deep trench (DT) mode for narrow and deep trenches, and a CD mode for linewidth and sidewall profiling. The 3D capability enables one tool for many applications where conventional scanning electron microscopy (SEM), scatterometry, and stylus profiler tools fall short: Gate etch/resist linewidth and sidewall cross-section profile, etch depth for high aspect ratio via, STI etch depth, 3D analysis for MUGFET multi-gate devices, pitch/CD/sidewall angle (SWA) verification for scatterometry targets, and post-CMP active recess. The AFM is an efficient tool for inline monitoring, rapid process improvement/development, and is a complementary addition to the dimension metrology family.


Archive | 2006

STI stressor integration for minimal phosphoric exposure and divot-free topography

Mark D. Hall; Peter J. Beckage; John J. Hackenberg; Toni D. Van Gompel


Archive | 2007

Stressor integration and method thereof

Paul A. Grudowski; Darren V. Goedekc; John J. Hackenberg


Archive | 2007

Method to improve source/drain parasitics in vertical devices

Leo Mathew; John J. Hackenberg; David C. Sing; Tab A. Stephens; Daniel Tekleab; Vishal P. Trivedi


Archive | 2008

Method of forming a semiconductor layer

Hunter J. Martinez; John J. Hackenberg; Jill Hildreth; R. Noble


Archive | 2005

Electronic device including a trench field isolation region and a process for forming the same

Michael D. Turner; John J. Hackenberg; Toni D. Van Gompel


Meeting Abstracts | 2006

Dual Substrate Orientation Integration for High Performance (110) PMOS

Gauri V. Karve; White Ted; Debby Eades; Mariam G. Sadaka; Greg Spencer; John J. Hackenberg; John Norbert; Tom Kropewnicki; Stefan Zollner; Pete Beckage; Jack Grant; R. Garcia; Bich-Yen Nguyen; Nigel Cave; Mark D. Hall; Jon Cheek; Suresh Venkatesan; C.T. Lin; I-Lu Wu


Archive | 2006

Method of forming a semiconductor isolation trench

Toni D. Van Gompel; John J. Hackenberg; Rode R. Mora; Suresh Venkatesan

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Mark D. Hall

Freescale Semiconductor

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