Lawrence Snyder

Bounds on minimax edge length for complete binary trees

Information is not transferred instantaneously; there is always a propagation delay before an output is available as an input to the next computational step. Propagation delay is a function of wire length, so we study the length of edges in planar graphs. We prove matching (to within a constant factor) upper and lower bounds on minimax edge length for four planar embedding problems for complete binary trees. (The results are summarized in Table 1.) Because trees are often subcircuits of larger circuits, these results imply general performance limits due to propagation delay. The results give important information for the popular technique of pipelining.

Minimum Edge Length Planar Embeddings of Trees

Valiant [1] showed how to embed any binary tree into the plane in linear area without crossovers. The edges in this embedding have a maximum length of 0(\( \sqrt {n} \)) With Paterson, we [2] showed that a complete binary tree can be embedded in the plane with maximum edge length of 0(\( \sqrt {n} \)/log n) and we argued the importance of short edge length for VLSI design and layout. Here we show that every binary tree can be embedded in the plane with all three properties: linear area, no crossovers, and 0(\( \sqrt {n} \)/log n) maximum edge length. This improves a result of Bhatt and Leiserson [3] — a graph with an n1/2-e separator theorem can be embedded (perhaps with crossovers) in linear area and with a maximum edge length of 0(\( \sqrt {n} \)) — for the case of binary trees. In the paper we also observe that Valiant’s result can be extended to the case of oriented trees [7].

Supercomputers and VLSI: The effect of large-scale integration on computer architecture

Publisher Summary This chapter discusses the economics of mass production, the geometry of the plane, the architecture of supercomputers and VLSI (Very-large-scale integration). The chapter provides a realistic idea of how much circuitry fits on a chip. This will be done in functional or architectural terms. The single-chip microprocessor is discussed. The chapter considers the consequences of using VLSI for computer architecture. The outcome of such analysis was that the benefits of VLSI, especially low cost, do not suggest a general trend toward single-chip computers. This surprising outcome motivated a more careful analysis of both the advantages and disadvantages of the technology. The Configurable, Highly Parallel (CHIP) computer was introduced as a specific instance of VLS1-compatible architecture; it was then examined in terms of its exploitation of the benefits of VLSI and its avoidance of the liabilities. To exploit the benefits of VLSI technology and simultaneously avoid its limitations require us to replace the familiar, tested architectural structures with new, imaginative architectures.

Recognition and selection of idioms for code optimization

SummaryIdioms are frequently occurring expressions that programmers use for logically primitive operations for which no primitive construct is available in the language. For example, in ALGOL-60 the expression abs(X − X ÷ 2 × 2) is idiomatic for parity of X. With optimization as a motive, two problems, idiom recognition and selection, are defined. Recognition is solved in O(n log n) time (worst case), O(n) time (average case) on a uniform cost RAM. Selection is solved in O(n) time. Ambiguity is solved in O(n2) time and is related to resolution theorem proving.

Compilation of data-driven programs for synchronous execution

We present algorithms that convert a class of parallel programs, called loop programs, from data-driven mode to synchronous mode. Such algorithms enable programmers to use a high-level, data-driven programming language without forfeiting the efficiency of a synchronous machine. We characterize loop programs for which conversion is possible in terms of sets of balancing equations and we present two conversion algorithms.

Configurable,Highly Parallel (CHiP) Approach For Signal Processing Applications

Between the conception of a real time signal processor and its functional, VLSI realization there is an enormous amount of effort devoted to designing, revising, optimizing and testing. Since the process is cumulative -- later work builds on previous work -- and since the activity becomes progressively more detailed, more constrained and more exacting, it follows that the global design parameters should be fully explored. Global design decisions, when correct, can have a greater effect on performance than many local optimiza-tions. When the decisions are wrong, they can cause continual difficulty. Accordingly, we propose a design methodology based on the Configurable, Highly Parallel (CHiP) architecture family1 that focuses on exploring global design parameters and is especially well suited to the VLSI implementation of signal processing systems.