Lazar Saranovac

Wireless distributed functional electrical stimulation system

BackgroundThe control of movement in humans is hierarchical and distributed and uses feedback. An assistive system could be best integrated into the therapy of a human with a central nervous system lesion if the system is controlled in a similar manner. Here, we present a novel wireless architecture and routing protocol for a distributed functional electrical stimulation system that enables control of movement.MethodsThe new system comprises a set of miniature battery-powered devices with stimulating and sensing functionality mounted on the body of the subject. The devices communicate wirelessly with one coordinator device, which is connected to a host computer. The control algorithm runs on the computer in open- or closed-loop form. A prototype of the system was designed using commercial, off-the-shelf components. The propagation characteristics of electromagnetic waves and the distributed nature of the system were considered during the development of a two-hop routing protocol, which was implemented in the prototype’s software.ResultsThe outcomes of this research include a novel system architecture and routing protocol and a functional prototype based on commercial, off-the-shelf components. A proof-of-concept study was performed on a hemiplegic subject with paresis of the right arm. The subject was tasked with generating a fully functional palmar grasp (closing of the fingers). One node was used to provide this movement, while a second node controlled the activation of extensor muscles to eliminate undesired wrist flexion. The system was tested with the open- and closed-loop control algorithms.ConclusionsThe system fulfilled technical and application requirements. The novel communication protocol enabled reliable real-time use of the system in both closed- and open-loop forms. The testing on a patient showed that the multi-node system could operate effectively to generate functional movement.

A Simple Algorithm for the Estimation of Phase Difference Between Two Sinusoidal Voltages

A simple algorithm (SAL) and a modified SAL (MSAL) for the estimation of the phase difference between two sine-wave signals are proposed. The results obtained by SAL and MSAL in simulations and on real samples are given. A comparison between the phase difference results estimated by MSAL, quadrature delay estimator (QDE), unbiased QDE (UQDE), three-parameter sine-fitting algorithm (3PSF), four-parameter sine-fitting algorithm (4PSF), and seven-parameter sine-fitting algorithm (7PSF) is presented. The requirements for the application of SAL and MSAL are analyzed.

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing need for domain-specific acceleration technologies, this paper describes a design methodology (i) to automatically generate a domain-specific coarse-grained array from a set of representative applications and (ii) to introduce limited forms of architectural generality to increase the likelihood that additional applications can be successfully mapped onto it. In particular, coarse-grained arrays generated using our approach are intended to be integrated into customizable processors that use application-specific instruction set extensions to accelerate performance and reduce energy; rather than implementing these extensions using application-specific integrated circuit (ASIC) logic, which lacks flexibility, they can be synthesized onto our reconfigurable array instead, allowing the processor to be used for a variety of applications in related domains. Results show that our array is around 2× slower and 15× larger than an ultimately efficient ASIC implementation, and thus far more efficient than fieldprogrammable gate arrays (FPGAs), which are known to be 3-4× slower and 20-40× larger. Additionally, we estimate that our array is usually around 2× larger and 2× slower than an accelerator synthesized using traditional datapath merging, which has, if any, very limited flexibility beyond the design set of DFGs.

Selective flexibility: breaking the rigidity of datapath merging

Hardware specialization is often the key to efficiency for programmable embedded systems, but comes at the expense of flexibility. This paper combines flexibility and efficiency in the design and synthesis of domain-specific datapaths. We merge all individual paths from the Data Flow Graphs (DFGs) of the target applications, leading to a minimal set of required resources; this set is organized into a column of physical operators and cloned, thus generating a domain-specific rectangular lattice. A bus-based FPGA-style interconnection network is then generated and dimensioned to meet the needs of the applications. Our results demonstrate that the lattice has good flexibility: DFGs that were not used as part of the datapath creation phase can be mapped onto it with high probability. Compared to an ASIC design of a single DFG, the speed of our domain-specific coarse-grained reconfigurable datapath is degraded by a factor up to 2×, compared to 3-4× for an FPGA; similarly, our lattice is up to 10× larger than an ASIC, compared to 20-40× for an FPGA. We estimate that our array is up to 6× larger than an ASIC accelerator, which is synthesized using datapath merging and has limited or null generality.

Comments on "New algorithm for measuring 50/60-Hz AC values based on the usage of slow A/D converters" and "Measuring of slowly changing AC signals without sample-and-hold circuit"

In this correspondence, the results of the original paper are commented on [ see ibid., vol. 49, p. 166-71, 2000 and vol. 49, p. 1245-48, 2000]. It is shown that conditions when the averaging formula is claimed to be valid are not correct, and that synchronization on the signal period level is required. Correction of these conditions is given.

60 GHz SiGe:C HBT Power Amplifier With 17.4 dBm Output Power and 16.3% PAE

Single stage cascode power amplifier for 60 GHz band is presented in this letter. Modeling methodology, together with effects of (im)proper local interconnect modeling on achievable output power is discussed. Design partitioning is proposed to reduce the complexity of EM models, while retaining the accuracy of simulation. Test chip was fabricated in a 0.25 μm BiCMOS SiGe:C HBT technology with 200/200 GHz, and measured on-wafer. Measurement results are in close agreement with simulation, validating our modeling approach. Saturated output power of 17.4 dBm and peak PAE of 16.3% was measured at 61.5 GHz. Small signal measurements indicate that the PA covers the whole unlicensed 60 GHz band.

Analysis of impact of FPGA routing architecture parameters on area and delay

FPGAs are increasingly replacing more expensive microprocessors and ASICs in a wide variety of applications. Their performance is limited mainly by the characteristics of the routing network. This paper presents a detailed study of the influence of the parameters defining an FPGA routing network on the routing area, the critical path delay, and the channel width required to place and route benchmark circuits. The goal was to find the set of parameter values providing maximal performance of the routing network. The results have shown that the trade-offs are inevitable.

Algorithm for EMG noise level approximation in ECG signals

Abstract In this paper, we introduce an approach for Electromyogram (EMG) noise level approximation in Electrocardiogram (ECG) signals. The stationary wavelet transform (SWT) is used to find efficient translation-invariant approximation of EMG noise. This is accomplished in the form of reference signal extracted as an estimation of the signal quality vs. EMG noise. The reference signal is built and then normalized after considering different heart rates and rhythms which increases its robustness and reliability to give accurate results regardless of input signal rhythm. Additionally, four applications of the extracted reference signal are suggested in this paper. For evaluation purposes both real EMG and artificial noises were used. The tested ECG signals are from MIT-BIH Arrhythmia Database Directory. The correlation coefficient between the added noise and the reference signal were computed for moving windows over the signal. Finally, the correlation between beats detection and reference signal was computed and presented. Reference signal gave high correlation with false positive values. Most false positives caused by EMG noise occur in intervals of greater amplitude reference signal and vice versa.

Digital realization of frequency insensitive phase shifter for reactive Var-Hour meters

The paper describes a digital realization of a circuit for an additional phase shift of /spl pi//2 between two input signals, with a constant amplification nondependent on frequency. The circuit is intended for measuring the reactive power and energy of electric networks. The solution is based on a coupled digital integrator and differentiator and the microcontroller application. The results of simulation and experiments show that the solution is applicable in standard (classes 2 and 3) and precise reactive meters (class 0.2).

Enhanced local tone mapping for detail preserving reproduction of high dynamic range images

Abstract Enhanced Local Tone Mapping (ELTM) is a flexible tone mapping operator designed to provide a good global and local contrast simultaneously over various test scenes. Also, it has intuitive and decoupled tuning interface, providing the user with full control over final image appearance. ELTM is based on detail/base layer decomposition compressing the base plane in both linear and logarithmic domain. This provides robustness to ELTM, while modified tone compression function provides good local contrast. Results were validated using set of images with various content, brightness and resolution. In this testing ELTM performed as the best tone mapping operator, among 7 state-of-the-art global and local tone mapping operators. Even better overall results are achieved by using proposed brightness control, to handle extreme scenes. Robustness and flexibility to achieve desired appearance makes ELTM suitable for applications where user experience is the primary concern as is the case with consumer electronics products.