James Harbin

A Wormhole NoC Protocol for Mixed Criticality Systems

Lack of scalability and difficulties in predicting the temporal behaviour of bus-based architectures has lead to the development of Network-on-Chip (NoC) protocols that provide a schedulable resource for moving data across multi-core platforms. Wormhole switching and credit-based flow control protocols have been used to support flit-level priority-preemptive link arbitration in NoCs, which leads to analysable temporal behaviour. In this paper we develop a new protocol (WPMC), based on the same family of protocols, that gives full support to mixed-criticality on-chip communications. WPMC is defined to give adequate partitioning between criticality levels, and to use resources efficiently. Analysis is developed and implementation aspects are considered. A cycle accurate simulator is used for scenario-based verification, and the effectiveness of the protocol and its scheduling model is evaluated via message-set generation.

Average and Worst-Case Latency Improvements in Mixed-Criticality Wormhole Networks-on-Chip

Mixed-criticality applications executing over a multiprocessor platform based on Network-on-Chip (NoC) exchange packets of different criticality levels through the same communication infrastructure, and transmission of a packet has potential impact over the latency of all the others. This paper presents NoC architectural improvements to output port arbitration and mode change signalling. The first aim is to improve the average latency of low-criticality packets following a mode change by allowing NoC arbiters to service them during cycles in which no high-criticality flows can be transmitted. The second aim is to reduce the worst-case latency of high-criticality packets transmitted by the NoC. The former objective improves the systems responsiveness, while the latter contributes to increased resource efficiency. The achieved improvements are evaluated, respectively, by cycle-accurate simulation and by schedulability analysis, showing full delivery of low-criticality packets following a criticality change, and achieving full schedulability in 8.2% more flow sets than the state of the art.

Bioinspired Load Balancing in Large-Scale WSNs Using Pheromone Signalling

Wireless sensor networks (WSNs) consist of multiple, distributed nodes each with limited resources. With their strict resource constraints and application-specific characteristics, WSNs contain many challenging tradeoffs. This paper proposes a bioinspired load balancing approach, based on pheromone signalling mechanisms, to solve the tradeoff between service availability and energy consumption. We explore the performance consequences of the pheromone-based load balancing approach using (1) a system-level simulator, (2) deployment of real sensor testbeds to provide a competitive analysis of these evaluation methodologies. The effectiveness of the proposed algorithm is evaluated with different scenario parameters and the required performance evaluation techniques are investigated on case studies based on sound sensors.

Runtime optimisation in WSNs for load balancing using pheromone signalling

Wireless Sensor Networks (WSNs) consist of multiple, distributed nodes each with limited resources. With their strict resource constraints and application-specific characteristics, WSNs contain many challenging trade-offs. This paper proposes a bio-inspired load balancing approach, based on pheromone signalling mechanisms, to solve the trade-off between service availability and energy consumption. We explore the performance consequences of the pheromone-based load balancing approach using: 1) a system-level simulator; 2) deployment of real sensor testbeds to provide a competitive analysis of these evaluation methodologies. The effectiveness of the proposed algorithm is evaluated with different scenario parameters and the required performance evaluation techniques are investigated on case studies based on sound sensors.

Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration

An increasingly time-consuming part of the design flow of on-chip multiprocessors is the simulation of the interconnect architecture. The accurate simulation of state-of-the art network-on-chip interconnects can take hours, and this process is repeated for each design iteration because it provides valuable insights on communication latencies that can greatly affect the overall performance of the system. In this article, we identify a time-predictable network-on-chip architecture and show that its timing behaviour can be predicted using models which are far less complex than the architecture itself. We then explore such a feature to produce simplified and lightweight simulation models that can produce latency figures with more than 90% accuracy and simulate more than 1,000 times faster when compared to a cycle-accurate model of the same interconnect.

Dynamic task remapping for power and latency performance improvement in priority-based non-preemptive Networks On Chip

In dynamic system-on-chip and multicore CPU applications, the communication patterns between tasks are not easy to characterise in advance. Dynamic task mapping is commonly used in Network-On-Chip (NoC) research in order to redistribute tasks around network processing elements at runtime in response to changes in network loading. Dynamic task mapping is anticipated to become more important as general purpose CPUs become massively multicore and system-on-chip (SoC) designs become more reconfigurable in their application usage patterns. Simultaneously, reducing NoC power consumption is a necessary consideration in the development of future scaleable and energy efficient NoC systems. The work illustrated here uses a dynamic metric which combines contention and the power consumption impact of task remapping decisions, in order to produce a non-preemptive NoC that can deliver as good or better latency as a preemptive NoC in a real application scenario, while reducing overall power consumption. The results obtained show a power consumption reduction of approximately 35% in an application case involving an autonomous vehicle application, and significant reductions in the latency of individual flows.

Wireless sensor network wormhole avoidance using disturbance-based routing schemes

The wormhole attack is an insidious attack on wireless sensor and ad-hoc networks which allows an attacker with only two malicious devices an unprecedented degree of control over network connectivity. It may be implemented without physical compromise of any existing node, and poses problems in terms of reliable detection, as the resulting network properties may be difficult to distinguish from genuine routing improvements via new connectivity. However, as a wormhole attempts to encourage route formation in its vicinity, under network load an active wormhole will generate significant congestion around its endpoints. This paper proposes a novel routing approach which attempts to detect situations which may produce the poor performance characteristic of an ongoing wormhole attack, by making nodes take account of disturbance (the impact of a forwarding commitment on their peers), and diversify routes to attempt to find a wormhole-free path and reduce the influence of the attacker. An example security-sensitive deployment scenario is proposed, and simulation of this scenario is used to evaluate relative performance and energy costs of static and dynamic disturbance-based routing schemes, showing the schemes deliver significant performance improvements over shortest path routing.

Network-on-Chip packet prioritisation based on instantaneous slack awareness

Arbitration policies and predictability enhancement measures typically employ packet priority as the decisive parameter. Though packet timeliness is a key attribute, Network-on-Chip designs rarely consider timeliness as a parameter mostly due to the impracticality of utilising time stamping which relay on the notion of a global time. In this paper, we introduce a low overhead approach where packets carry a slack value, which would notify the router of the latency the packet can suffer without any adverse effects. This would enable routers to service late packets (even lower priority ones) by trading the expendable time associated with the high priority packets hence improving overall quality of service. Utilising a Hardware Description Language coded prototype, we demonstrate the effectiveness of the technique and quantify the associated hardware overhead.

Fast transaction-level dynamic power consumption modelling in priority preemptive wormhole switching networks on chip

This paper specifies an architecture for power consumption modelling integrated within cycle-approximate transaction level modelling for network-on-chip (NoC) simulation. NoC simulations during design validation have traditionally been limited to very short durations, due to the necessity to perform cycle-accurate simulation to represent fully the low level system simulated. Due to the high proportion of overall system power that may be consumed by a busy NoC, high-fidelity NoC power modelling is especially important to accurately assess the effectiveness of link coding and other strategies to reduce NoC power consumption. The paper describes the extension of a cycle-approximate TLM methodology to encompass power modelling in NoCs, considering its operation with real application traffic. The proposed scheme avoids modelling of flit-by-flit progress during non-preemptive periods of packet transmission. The simulation performance and accuracy are contrasted with theoretical models and a flit-by-flit scheme (in which each flow control digit passing along a bus wire is simulated). The power consumption reduction delivered by encoding schemes such as bus-invert coding are considered and compared with analytical models to verify the correct performance of the simulation models.

Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

The simulation of interconnect architectures can be a time-consuming part of the design flow of on-chip multiprocessors. Accurate simulation of state-of-the art network-on-chip interconnects can take several hours for realistic application examples, and this process must be repeated for each design iteration because the interactions between design choices can greatly affect the overall throughput and latency performance of the system. This paper presents a series of network-on-chip transaction-level model (TLM) algorithms that provide a highly abstracted view of the process of data transmission in priority preemptive and non-preemptive networks-on-chip, which permit a major reduction in simulation event count. These simulation models are tested using two realistic application case studies and with synthetic traffic. Results presented demonstrate that these lightweight TLM simulation models can produce latency figures accurate to within mere flits for the majority of flows, and more than 93% accurate link dynamic power consumption modelling, while simulating 2.5 to 3 orders of magnitude faster when compared to a cycle-accurate model of the same interconnect.